Cleanup

physical-computation · May 27, 2020 · 97ec401 · 97ec401
1 parent 0944c51
commit 97ec401
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/verilog/CSR.v b/verilog/CSR.v
@@ -39,7 +39,7 @@
 /*
  *	Description:
  *
- *		This module implements the control and status registers (CSRs) using the iCE40UP5K's single-port RAM (SPRAM)
+ *		This module implements the control and status registers (CSRs).
  */