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IR: rename _VBic -> _VAndn
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to be consistent with the scalar _Andn opcode, which is specifically named _Andn
and not _Bic.

noticed while reviewing AVX patches

Signed-off-by: Alyssa Rosenzweig <[email protected]>
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@alyssarosenzweig
alyssarosenzweig committed Jun 18, 2024
1 parent 89b05a2 commit 01da597
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Showing 4 changed files with 11 additions and 11 deletions.
2 changes: 1 addition & 1 deletion FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -194,7 +194,7 @@ DEF_UNOP(VNeg, neg, false)
DEF_UNOP(VFNeg, fneg, false)

DEF_BITOP(VAnd, and_)
DEF_BITOP(VBic, bic)
DEF_BITOP(VAndn, bic)
DEF_BITOP(VOr, orr)
DEF_BITOP(VXor, eor)

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8 changes: 4 additions & 4 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5656,7 +5656,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
{0x52, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFRSQRT, 4>},
{0x53, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFRECP, 4>},
{0x54, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VAND, 16>},
{0x55, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
{0x55, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VANDN, 8>},
{0x56, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VOR, 16>},
{0x57, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VXOR, 16>},
{0x58, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFADD, 4>},
Expand Down Expand Up @@ -5702,7 +5702,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
{0xDC, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUQADD, 1>},
{0xDD, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUQADD, 2>},
{0xDE, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUMAX, 1>},
{0xDF, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
{0xDF, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VANDN, 8>},
{0xE0, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VURAVG, 1>},
{0xE1, 1, &OpDispatchBuilder::PSRAOp<2>},
{0xE2, 1, &OpDispatchBuilder::PSRAOp<4>},
Expand Down Expand Up @@ -5945,7 +5945,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
{0x50, 1, &OpDispatchBuilder::MOVMSKOp<8>},
{0x51, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFSQRT, 8>},
{0x54, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VAND, 16>},
{0x55, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
{0x55, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VANDN, 8>},
{0x56, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VOR, 16>},
{0x57, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VXOR, 16>},
{0x58, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFADD, 8>},
Expand Down Expand Up @@ -6002,7 +6002,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
{0xDC, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUQADD, 1>},
{0xDD, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUQADD, 2>},
{0xDE, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VUMAX, 1>},
{0xDF, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>},
{0xDF, 1, &OpDispatchBuilder::VectorALUROp<IR::OP_VANDN, 8>},
{0xE0, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VURAVG, 1>},
{0xE1, 1, &OpDispatchBuilder::PSRAOp<2>},
{0xE2, 1, &OpDispatchBuilder::PSRAOp<4>},
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10 changes: 5 additions & 5 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
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Expand Up @@ -386,7 +386,7 @@ void OpDispatchBuilder::VectorALUROp(OpcodeArgs) {
VectorALUROpImpl(Op, IROp, ElementSize);
}

template void OpDispatchBuilder::VectorALUROp<IR::OP_VBIC, 8>(OpcodeArgs);
template void OpDispatchBuilder::VectorALUROp<IR::OP_VANDN, 8>(OpcodeArgs);
template void OpDispatchBuilder::VectorALUROp<IR::OP_VFSUB, 4>(OpcodeArgs);
template void OpDispatchBuilder::VectorALUROp<IR::OP_VFSUB, 8>(OpcodeArgs);

Expand Down Expand Up @@ -1482,7 +1482,7 @@ void OpDispatchBuilder::VANDNOp(OpcodeArgs) {

Ref Src1 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
Ref Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags);
Ref Dest = _VBic(SrcSize, SrcSize, Src2, Src1);
Ref Dest = _VAndn(SrcSize, SrcSize, Src2, Src1);

StoreResult(FPRClass, Op, Dest, -1);
}
Expand Down Expand Up @@ -1724,7 +1724,7 @@ Ref OpDispatchBuilder::PSIGNImpl(OpcodeArgs, size_t ElementSize, Ref Src1, Ref S
Ref CmpLT = _VCMPLTZ(Size, ElementSize, Src2);
Ref CmpEQ = _VCMPEQZ(Size, ElementSize, Src2);
auto BSLResult = _VBSL(Size, CmpLT, NegVec, Src1);
return _VBic(Size, Size, BSLResult, CmpEQ);
return _VAndn(Size, Size, BSLResult, CmpEQ);
}
}

Expand Down Expand Up @@ -4087,7 +4087,7 @@ void OpDispatchBuilder::PTestOp(OpcodeArgs) {
Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);

Ref Test1 = _VAnd(Size, 1, Dest, Src);
Ref Test2 = _VBic(Size, 1, Src, Dest);
Ref Test2 = _VAndn(Size, 1, Src, Dest);

// Element size must be less than 32-bit for the sign bit tricks.
Test1 = _VUMaxV(Size, 2, Test1);
Expand Down Expand Up @@ -4124,7 +4124,7 @@ void OpDispatchBuilder::VTESTOpImpl(OpcodeArgs, size_t ElementSize) {
Ref Mask = _VDupFromGPR(SrcSize, ElementSize, _Constant(MaskConstant));

Ref AndTest = _VAnd(SrcSize, 1, Src2, Src1);
Ref AndNotTest = _VBic(SrcSize, 1, Src2, Src1);
Ref AndNotTest = _VAndn(SrcSize, 1, Src2, Src1);

Ref MaskedAnd = _VAnd(SrcSize, 1, AndTest, Mask);
Ref MaskedAndNot = _VAnd(SrcSize, 1, AndNotTest, Mask);
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2 changes: 1 addition & 1 deletion FEXCore/Source/Interface/IR/IR.json
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Expand Up @@ -1917,7 +1917,7 @@
"NumElements": "RegisterSize / ElementSize"
},

"FPR = VBic u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
"FPR = VAndn u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
"DestSize": "RegisterSize",
"NumElements": "RegisterSize / ElementSize"
},
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