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InstcountCI: Update
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@Sonicadvance1
Sonicadvance1 committed Jul 20, 2024
1 parent 95b15d7 commit 4fffe68
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Showing 3 changed files with 67 additions and 81 deletions.
64 changes: 29 additions & 35 deletions unittests/InstructionCountCI/FlagM/SecondaryGroup.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1186,7 +1186,7 @@
]
},
"fxsave [rax]": {
"ExpectedInstructionCount": 56,
"ExpectedInstructionCount": 52,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1296]",
Expand Down Expand Up @@ -1236,12 +1236,8 @@
"str q29, [x4, #368]",
"str q30, [x4, #384]",
"str q31, [x4, #400]",
"mov w20, #0x1f80",
"mrs x21, fpcr",
"ubfx x21, x21, #22, #3",
"rbit w0, w21",
"bfi x21, x0, #30, #2",
"bfi w20, w21, #13, #3",
"ldr w20, [x28, #940]",
"and w20, w20, #0xffc0",
"str w20, [x4, #24]",
"mov w20, #0xffff",
"str w20, [x4, #28]"
Expand All @@ -1262,7 +1258,7 @@
]
},
"fxrstor [rax]": {
"ExpectedInstructionCount": 56,
"ExpectedInstructionCount": 58,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
Expand Down Expand Up @@ -1304,12 +1300,14 @@
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"ldr w21, [x4, #24]",
"ubfx w21, w21, #13, #3",
"rbit w1, w21",
"and w21, w21, #0xffc0",
"str w21, [x28, #940]",
"ubfx w22, w21, #13, #3",
"rbit w1, w22",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x21, #2",
"lsr x1, x22, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0",
"strb w20, [x28, #1298]",
Expand Down Expand Up @@ -1338,16 +1336,18 @@
]
},
"ldmxcsr [rax]": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 11,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"ubfx w20, w20, #13, #3",
"rbit w1, w20",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x20, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0"
]
Expand All @@ -1368,15 +1368,11 @@
]
},
"stmxcsr [rax]": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 3,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"mov w20, #0x1f80",
"mrs x21, fpcr",
"ubfx x21, x21, #22, #3",
"rbit w0, w21",
"bfi x21, x0, #30, #2",
"bfi w20, w21, #13, #3",
"ldr w20, [x28, #940]",
"and w20, w20, #0xffc0",
"str w20, [x4]"
]
},
Expand All @@ -1396,7 +1392,7 @@
]
},
"xsave [rax]": {
"ExpectedInstructionCount": 102,
"ExpectedInstructionCount": 98,
"Comment": "GROUP15 0x0F 0xAE /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
Expand Down Expand Up @@ -1489,13 +1485,9 @@
"str q2, [x4, #816]",
"ubfx x20, x4, #1, #2",
"cbnz x20, #+0x8",
"b #+0x28",
"mov w20, #0x1f80",
"mrs x21, fpcr",
"ubfx x21, x21, #22, #3",
"rbit w0, w21",
"bfi x21, x0, #30, #2",
"bfi w20, w21, #13, #3",
"b #+0x18",
"ldr w20, [x28, #940]",
"and w20, w20, #0xffc0",
"str w20, [x4, #24]",
"mov w20, #0xffff",
"str w20, [x4, #28]",
Expand All @@ -1511,7 +1503,7 @@
]
},
"xrstor [rax]": {
"ExpectedInstructionCount": 165,
"ExpectedInstructionCount": 167,
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
"sub sp, sp, #0x40 (64)",
Expand Down Expand Up @@ -1667,14 +1659,16 @@
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #2",
"cbnz x20, #+0x8",
"b #+0x2c",
"b #+0x34",
"ldr w20, [x4, #24]",
"ubfx w20, w20, #13, #3",
"rbit w1, w20",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x20, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0",
"b #+0x4",
Expand Down
64 changes: 29 additions & 35 deletions unittests/InstructionCountCI/SecondaryGroup.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1370,7 +1370,7 @@
]
},
"fxsave [rax]": {
"ExpectedInstructionCount": 56,
"ExpectedInstructionCount": 52,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1296]",
Expand Down Expand Up @@ -1420,12 +1420,8 @@
"str q29, [x4, #368]",
"str q30, [x4, #384]",
"str q31, [x4, #400]",
"mov w20, #0x1f80",
"mrs x21, fpcr",
"ubfx x21, x21, #22, #3",
"rbit w0, w21",
"bfi x21, x0, #30, #2",
"bfi w20, w21, #13, #3",
"ldr w20, [x28, #940]",
"and w20, w20, #0xffc0",
"str w20, [x4, #24]",
"mov w20, #0xffff",
"str w20, [x4, #28]"
Expand All @@ -1446,7 +1442,7 @@
]
},
"fxrstor [rax]": {
"ExpectedInstructionCount": 56,
"ExpectedInstructionCount": 58,
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
Expand Down Expand Up @@ -1488,12 +1484,14 @@
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"ldr w21, [x4, #24]",
"ubfx w21, w21, #13, #3",
"rbit w1, w21",
"and w21, w21, #0xffc0",
"str w21, [x28, #940]",
"ubfx w22, w21, #13, #3",
"rbit w1, w22",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x21, #2",
"lsr x1, x22, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0",
"strb w20, [x28, #1298]",
Expand Down Expand Up @@ -1522,16 +1520,18 @@
]
},
"ldmxcsr [rax]": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 11,
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"ubfx w20, w20, #13, #3",
"rbit w1, w20",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x20, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0"
]
Expand All @@ -1552,15 +1552,11 @@
]
},
"stmxcsr [rax]": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 3,
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"mov w20, #0x1f80",
"mrs x21, fpcr",
"ubfx x21, x21, #22, #3",
"rbit w0, w21",
"bfi x21, x0, #30, #2",
"bfi w20, w21, #13, #3",
"ldr w20, [x28, #940]",
"and w20, w20, #0xffc0",
"str w20, [x4]"
]
},
Expand All @@ -1580,7 +1576,7 @@
]
},
"xsave [rax]": {
"ExpectedInstructionCount": 102,
"ExpectedInstructionCount": 98,
"Comment": "GROUP15 0x0F 0xAE /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
Expand Down Expand Up @@ -1673,13 +1669,9 @@
"str q2, [x4, #816]",
"ubfx x20, x4, #1, #2",
"cbnz x20, #+0x8",
"b #+0x28",
"mov w20, #0x1f80",
"mrs x21, fpcr",
"ubfx x21, x21, #22, #3",
"rbit w0, w21",
"bfi x21, x0, #30, #2",
"bfi w20, w21, #13, #3",
"b #+0x18",
"ldr w20, [x28, #940]",
"and w20, w20, #0xffc0",
"str w20, [x4, #24]",
"mov w20, #0xffff",
"str w20, [x4, #28]",
Expand All @@ -1695,7 +1687,7 @@
]
},
"xrstor [rax]": {
"ExpectedInstructionCount": 165,
"ExpectedInstructionCount": 167,
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
"sub sp, sp, #0x40 (64)",
Expand Down Expand Up @@ -1851,14 +1843,16 @@
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #2",
"cbnz x20, #+0x8",
"b #+0x2c",
"b #+0x34",
"ldr w20, [x4, #24]",
"ubfx w20, w20, #13, #3",
"rbit w1, w20",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x20, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0",
"b #+0x4",
Expand Down
20 changes: 9 additions & 11 deletions unittests/InstructionCountCI/VEX_map_group.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -578,34 +578,32 @@
]
},
"vldmxcsr [rax]": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 11,
"Comment": [
"Map group 15 0b010"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"ubfx w20, w20, #13, #3",
"rbit w1, w20",
"and w20, w20, #0xffc0",
"str w20, [x28, #940]",
"ubfx w21, w20, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x20, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0"
]
},
"vstmxcsr [rax]": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 3,
"Comment": [
"Map group 15 0b011"
],
"ExpectedArm64ASM": [
"mov w20, #0x1f80",
"mrs x21, fpcr",
"ubfx x21, x21, #22, #3",
"rbit w0, w21",
"bfi x21, x0, #30, #2",
"bfi w20, w21, #13, #3",
"ldr w20, [x28, #940]",
"and w20, w20, #0xffc0",
"str w20, [x4]"
]
},
Expand Down

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