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Merge pull request FEX-Emu#3820 from alyssarosenzweig/ir/drop-deferred
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Drop deferred flag infrastructure
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@Sonicadvance1
Sonicadvance1 authored Jul 10, 2024
2 parents 991c694 + 837bccb commit 72d6c8e
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Showing 9 changed files with 1,306 additions and 1,719 deletions.
58 changes: 28 additions & 30 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1174,7 +1174,7 @@ void OpDispatchBuilder::CMPOp(OpcodeArgs) {
// Result isn't stored in result, only writes to flags
Ref Src = LoadSource(GPRClass, Op, Op->Src[SrcIndex], Op->Flags, {.AllowUpperGarbage = true});
Ref Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = true});
GenerateFlags_SUB(Op, Dest, Src);
CalculateFlags_SUB(GetSrcSize(Op), Dest, Src);
}

void OpDispatchBuilder::CQOOp(OpcodeArgs) {
Expand Down Expand Up @@ -1482,7 +1482,7 @@ void OpDispatchBuilder::SHLImmediateOp(OpcodeArgs) {
Ref Src = _Constant(Size, Shift);
Ref Result = _Lshl(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src);

GenerateFlags_ShiftLeftImmediate(Op, Result, Dest, Shift);
CalculateFlags_ShiftLeftImmediate(GetSrcSize(Op), Result, Dest, Shift);
CalculateDeferredFlags();
StoreResult(GPRClass, Op, Result, -1);
}
Expand All @@ -1506,7 +1506,7 @@ void OpDispatchBuilder::SHRImmediateOp(OpcodeArgs) {
Ref Src = _Constant(Size, Shift);
auto ALUOp = _Lshr(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src);

GenerateFlags_ShiftRightImmediate(Op, ALUOp, Dest, Shift);
CalculateFlags_ShiftRightImmediate(GetSrcSize(Op), ALUOp, Dest, Shift);
CalculateDeferredFlags();
StoreResult(GPRClass, Op, ALUOp, -1);
}
Expand Down Expand Up @@ -1575,7 +1575,7 @@ void OpDispatchBuilder::SHLDImmediateOp(OpcodeArgs) {
Res = _Extr(OpSizeFromSrc(Op), Dest, Src, Size - Shift);
}

GenerateFlags_ShiftLeftImmediate(Op, Res, Dest, Shift);
CalculateFlags_ShiftLeftImmediate(GetSrcSize(Op), Res, Dest, Shift);
CalculateDeferredFlags();
StoreResult(GPRClass, Op, Res, -1);
} else if (Shift == 0 && Size == 32) {
Expand Down Expand Up @@ -1641,7 +1641,7 @@ void OpDispatchBuilder::SHRDImmediateOp(OpcodeArgs) {
}

StoreResult(GPRClass, Op, Res, -1);
GenerateFlags_ShiftRightDoubleImmediate(Op, Res, Dest, Shift);
CalculateFlags_ShiftRightDoubleImmediate(GetSrcSize(Op), Res, Dest, Shift);
} else if (Shift == 0 && Size == 32) {
// Ensure Zext still occurs
StoreResult(GPRClass, Op, Dest, -1);
Expand All @@ -1667,7 +1667,7 @@ void OpDispatchBuilder::ASHROp(OpcodeArgs) {
uint64_t Shift = LoadConstantShift(Op, SHR1Bit);
Ref Result = _Ashr(IR::SizeToOpSize(OpSize), Dest, _Constant(Shift));

GenerateFlags_SignShiftRightImmediate(Op, Result, Dest, Shift);
CalculateFlags_SignShiftRightImmediate(GetSrcSize(Op), Result, Dest, Shift);
CalculateDeferredFlags();
StoreResult(GPRClass, Op, Result, -1);
} else {
Expand Down Expand Up @@ -1747,7 +1747,7 @@ void OpDispatchBuilder::ANDNBMIOp(OpcodeArgs) {
auto Dest = _Andn(OpSizeFromSrc(Op), Src2, Src1);

StoreResult(GPRClass, Op, Dest, -1);
GenerateFlags_Logical(Op, Dest, Src1, Src2);
CalculateFlags_Logical(GetSrcSize(Op), Dest, Src1, Src2);
}

void OpDispatchBuilder::BEXTRBMIOp(OpcodeArgs) {
Expand Down Expand Up @@ -1787,7 +1787,7 @@ void OpDispatchBuilder::BEXTRBMIOp(OpcodeArgs) {
// Finally store the result.
StoreResult(GPRClass, Op, Dest, -1);

GenerateFlags_BEXTR(Op, Dest);
CalculateFlags_BEXTR(Dest);
}

void OpDispatchBuilder::BLSIBMIOp(OpcodeArgs) {
Expand All @@ -1802,7 +1802,7 @@ void OpDispatchBuilder::BLSIBMIOp(OpcodeArgs) {
// ...and we're done. Painless!
StoreResult(GPRClass, Op, Result, -1);

GenerateFlags_BLSI(Op, Result);
CalculateFlags_BLSI(GetSrcSize(Op), Result);
}

void OpDispatchBuilder::BLSMSKBMIOp(OpcodeArgs) {
Expand All @@ -1814,7 +1814,7 @@ void OpDispatchBuilder::BLSMSKBMIOp(OpcodeArgs) {
auto Result = _Xor(Size, _Sub(Size, Src, _Constant(1)), Src);

StoreResult(GPRClass, Op, Result, -1);
GenerateFlags_BLSMSK(Op, Result, Src);
CalculateFlags_BLSMSK(GetSrcSize(Op), Result, Src);
}

void OpDispatchBuilder::BLSRBMIOp(OpcodeArgs) {
Expand All @@ -1826,7 +1826,7 @@ void OpDispatchBuilder::BLSRBMIOp(OpcodeArgs) {
auto Result = _And(Size, _Sub(Size, Src, _Constant(1)), Src);
StoreResult(GPRClass, Op, Result, -1);

GenerateFlags_BLSR(Op, Result, Src);
CalculateFlags_BLSR(GetSrcSize(Op), Result, Src);
}

// Handles SARX, SHLX, and SHRX
Expand Down Expand Up @@ -1882,7 +1882,7 @@ void OpDispatchBuilder::BZHI(OpcodeArgs) {
auto Zero = _Constant(0);
auto One = _Constant(1);
auto CF = _NZCVSelect(OpSize::i32Bit, CondClassType {COND_NEQ}, One, Zero);
GenerateFlags_BZHI(Op, Result, CF);
CalculateFlags_BZHI(Size, Result, CF);
}

void OpDispatchBuilder::RORX(OpcodeArgs) {
Expand Down Expand Up @@ -2608,7 +2608,7 @@ void OpDispatchBuilder::IMUL1SrcOp(OpcodeArgs) {
}

StoreResult(GPRClass, Op, Dest, -1);
GenerateFlags_MUL(Op, Dest, ResultHigh);
CalculateFlags_MUL(Size, Dest, ResultHigh);
}

void OpDispatchBuilder::IMUL2SrcOp(OpcodeArgs) {
Expand Down Expand Up @@ -2646,7 +2646,7 @@ void OpDispatchBuilder::IMUL2SrcOp(OpcodeArgs) {
}

StoreResult(GPRClass, Op, Dest, -1);
GenerateFlags_MUL(Op, Dest, ResultHigh);
CalculateFlags_MUL(Size, Dest, ResultHigh);
}

void OpDispatchBuilder::IMULOp(OpcodeArgs) {
Expand Down Expand Up @@ -2697,7 +2697,7 @@ void OpDispatchBuilder::IMULOp(OpcodeArgs) {
StoreGPRRegister(X86State::REG_RDX, ResultHigh);
}

GenerateFlags_MUL(Op, Result, ResultHigh);
CalculateFlags_MUL(Size, Result, ResultHigh);
}

void OpDispatchBuilder::MULOp(OpcodeArgs) {
Expand Down Expand Up @@ -2743,7 +2743,7 @@ void OpDispatchBuilder::MULOp(OpcodeArgs) {
StoreGPRRegister(X86State::REG_RDX, ResultHigh);
}

GenerateFlags_UMUL(Op, ResultHigh);
CalculateFlags_UMUL(ResultHigh);
}

void OpDispatchBuilder::NOTOp(OpcodeArgs) {
Expand Down Expand Up @@ -2824,7 +2824,7 @@ void OpDispatchBuilder::PopcountOp(OpcodeArgs) {
Src = _Popcount(OpSizeFromSrc(Op), Src);
StoreResult(GPRClass, Op, Src, -1);

GenerateFlags_POPCOUNT(Op, Src);
CalculateFlags_POPCOUNT(Src);
}

Ref OpDispatchBuilder::CalculateAFForDecimal(Ref A) {
Expand Down Expand Up @@ -3332,7 +3332,7 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) {
auto Src1 = _LoadMemAutoTSO(GPRClass, Size, Dest_RDI, Size);
auto Src2 = _LoadMemAutoTSO(GPRClass, Size, Dest_RSI, Size);

GenerateFlags_SUB(Op, Src2, Src1);
CalculateFlags_SUB(GetSrcSize(Op), Src2, Src1);

auto PtrDir = LoadDir(Size);

Expand Down Expand Up @@ -3421,7 +3421,7 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) {
// Grab the sources from the last iteration so we can set flags.
auto Src1 = _LoadRegister(Core::CPUState::PF_AS_GREG, GPRClass, CTX->GetGPRSize());
auto Src2 = _LoadRegister(Core::CPUState::AF_AS_GREG, GPRClass, CTX->GetGPRSize());
GenerateFlags_SUB(Op, Src2, Src1);
CalculateFlags_SUB(GetSrcSize(Op), Src2, Src1);
}
auto Jump_ = Jump();

Expand Down Expand Up @@ -3532,7 +3532,7 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) {
auto Src1 = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true});
auto Src2 = _LoadMemAutoTSO(GPRClass, Size, Dest_RDI, Size);

GenerateFlags_SUB(Op, Src1, Src2);
CalculateFlags_SUB(GetSrcSize(Op), Src1, Src2);

// Offset the pointer
Ref TailDest_RDI = LoadGPRRegister(X86State::REG_RDI);
Expand Down Expand Up @@ -3570,7 +3570,7 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) {
auto Src1 = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true});
auto Src2 = _LoadMemAutoTSO(GPRClass, Size, Dest_RDI, Size);

GenerateFlags_SUB(Op, Src1, Src2);
CalculateFlags_SUB(GetSrcSize(Op), Src1, Src2);

// Calculate flags early.
CalculateDeferredFlags();
Expand Down Expand Up @@ -3871,7 +3871,7 @@ void OpDispatchBuilder::CMPXCHGOp(OpcodeArgs) {
}

// Compare RAX with the destination, setting flags accordingly.
GenerateFlags_SUB(Op, Src3Lower, Src1Lower);
CalculateFlags_SUB(GetSrcSize(Op), Src3Lower, Src1Lower);
CalculateDeferredFlags();

if (!Trivial) {
Expand Down Expand Up @@ -3925,7 +3925,7 @@ void OpDispatchBuilder::CMPXCHGOp(OpcodeArgs) {
Size = 8;
}

GenerateFlags_SUB(Op, Src3Lower, CASResult);
CalculateFlags_SUB(GetSrcSize(Op), Src3Lower, CASResult);
CalculateDeferredFlags();

// RAX gets the result of the CAS op
Expand Down Expand Up @@ -4003,8 +4003,6 @@ void OpDispatchBuilder::BeginFunction(uint64_t RIP, const fextl::vector<FEXCore:
auto Block = GetNewJumpBlock(RIP);
SetCurrentCodeBlock(Block);
IRHeader.first->Blocks = Block->Wrapped(DualListData.ListBegin());

LOGMAN_THROW_A_FMT(IsDeferredFlagsStored(), "Something failed to calculate flags and now we began with invalid state");
}

void OpDispatchBuilder::Finalize() {
Expand Down Expand Up @@ -4594,7 +4592,7 @@ void OpDispatchBuilder::ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCor

auto Result = _Constant(0);
StoreResult(GPRClass, Op, Result, -1);
GenerateFlags_Logical(Op, Result, Result, Result);
CalculateFlags_Logical(GetSrcSize(Op), Result, Result, Result);
return;
}

Expand Down Expand Up @@ -4631,7 +4629,7 @@ void OpDispatchBuilder::ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCor
case FEXCore::IR::IROps::OP_SUB: Result = CalculateFlags_SUB(Size, Dest, Src); break;
case FEXCore::IR::IROps::OP_XOR:
case FEXCore::IR::IROps::OP_OR: {
GenerateFlags_Logical(Op, Result, Dest, Src);
CalculateFlags_Logical(Size, Result, Dest, Src);
break;
}
case FEXCore::IR::IROps::OP_ANDWITHFLAGS: {
Expand Down Expand Up @@ -4766,7 +4764,7 @@ void OpDispatchBuilder::TZCNT(OpcodeArgs) {
Src = _FindTrailingZeroes(OpSizeFromSrc(Op), Src);
StoreResult(GPRClass, Op, Src, -1);

GenerateFlags_ZCNT(Op, Src);
CalculateFlags_ZCNT(GetSrcSize(Op), Src);
}

void OpDispatchBuilder::LZCNT(OpcodeArgs) {
Expand All @@ -4775,7 +4773,7 @@ void OpDispatchBuilder::LZCNT(OpcodeArgs) {

auto Res = _CountLeadingZeroes(OpSizeFromSrc(Op), Src);
StoreResult(GPRClass, Op, Res, -1);
GenerateFlags_ZCNT(Op, Res);
CalculateFlags_ZCNT(GetSrcSize(Op), Res);
}

void OpDispatchBuilder::MOVBEOp(OpcodeArgs) {
Expand Down Expand Up @@ -4895,7 +4893,7 @@ void OpDispatchBuilder::RDRANDOp(OpcodeArgs) {
auto [Result_Lower, Result_Upper] = ExtractPair(OpSize::i64Bit, Res);

StoreResult(GPRClass, Op, Result_Lower, -1);
GenerateFlags_RDRAND(Op, Result_Upper);
CalculateFlags_RDRAND(Result_Upper);
}


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