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versal: GT column detritus
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@wanda-phi
wanda-phi committed Dec 17, 2024
1 parent f141044 commit cf1c3a5
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Showing 6 changed files with 204 additions and 4 deletions.
37 changes: 37 additions & 0 deletions prjcombine_versal/src/expand.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -539,6 +539,41 @@ impl Expander<'_> {
}
}

fn fill_lgt(&mut self) {
for (dieid, grid) in &self.grids {
let mut die = self.egrid.die_mut(dieid);
let col = die.cols().next().unwrap();
let ps_height = grid.get_ps_height();
for reg in grid.regs() {
let row = grid.row_reg_bot(reg);
if row.to_idx() < ps_height {
continue;
}
let crds: [_; Grid::ROWS_PER_REG] = core::array::from_fn(|dy| (col, row + dy));
die.add_xnode(crds[0], "SYSMON_SAT.LGT", &crds);
die.add_xnode(crds[0], "DPLL.LGT", &crds);
// TODO: actual GT
}
}
}

fn fill_rgt(&mut self) {
for (dieid, grid) in &self.grids {
if !matches!(grid.right, RightKind::Gt(_) | RightKind::HNicX) {
continue;
}
let mut die = self.egrid.die_mut(dieid);
let col = die.cols().next_back().unwrap();
for reg in grid.regs() {
let row = grid.row_reg_bot(reg);
let crds: [_; Grid::ROWS_PER_REG] = core::array::from_fn(|dy| (col, row + dy));
die.add_xnode(crds[0], "SYSMON_SAT.RGT", &crds);
die.add_xnode(crds[0], "DPLL.RGT", &crds);
// TODO: actual GT
}
}
}

fn fill_clkroot(&mut self) {
for (dieid, grid) in &self.grids {
let mut die = self.egrid.die_mut(dieid);
Expand Down Expand Up @@ -583,6 +618,8 @@ pub fn expand_grid<'a>(
expander.fill_uram();
expander.fill_hard();
expander.fill_vnoc();
expander.fill_lgt();
expander.fill_rgt();
expander.fill_clkroot();
expander.egrid.finish();

Expand Down
37 changes: 37 additions & 0 deletions prjcombine_versal_naming/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,8 @@ pub struct DeviceNaming {
pub struct DieNaming {
pub hdio: BTreeMap<(ColId, RegId), HdioNaming>,
pub sysmon_sat_vnoc: BTreeMap<(ColId, RegId), (u32, u32)>,
pub sysmon_sat_gt: BTreeMap<(ColId, RegId), (u32, u32)>,
pub dpll_gt: BTreeMap<(ColId, RegId), (u32, u32)>,
pub vnoc2: BTreeMap<(ColId, RegId), VNoc2Naming>,
}

Expand Down Expand Up @@ -2383,6 +2385,41 @@ pub fn name_device<'a>(
let (sx, sy) = dev_naming.die[die.die].sysmon_sat_vnoc[&(col, reg)];
nnode.add_bel(0, vnoc_grid.name_manual("SYSMON_SAT", die.die, sx, sy));
}
"SYSMON_SAT.LGT" | "SYSMON_SAT.RGT" => {
let bt = if grid.is_reg_top(reg) { "TOP" } else { "BOT" };
let nnode = ngrid.name_node(
nloc,
kind,
[int_grid.name(
&format!("AMS_SAT_GT_{bt}_TILE"),
die.die,
col,
ColSide::Left,
row + 19,
0,
0,
)],
);
let (sx, sy) = dev_naming.die[die.die].sysmon_sat_gt[&(col, reg)];
nnode.add_bel(0, vnoc_grid.name_manual("SYSMON_SAT", die.die, sx, sy));
}
"DPLL.LGT" | "DPLL.RGT" => {
let nnode = ngrid.name_node(
nloc,
kind,
[int_grid.name(
"CMT_DPLL",
die.die,
col,
ColSide::Left,
row + 7,
0,
0,
)],
);
let (sx, sy) = dev_naming.die[die.die].dpll_gt[&(col, reg)];
nnode.add_bel(0, vnoc_grid.name_manual("DPLL", die.die, sx, sy));
}

_ => panic!("how to {kind}"),
}
Expand Down
34 changes: 34 additions & 0 deletions prjcombine_versal_rd2db/src/grid.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -419,6 +419,37 @@ fn get_vnoc_naming(int: &IntGrid, naming: &mut DieNaming, is_vnoc2_scan_offset:
}
}

fn get_gt_naming(int: &IntGrid, naming: &mut DieNaming) {
for tkn in [
"AMS_SAT_GT_BOT_TILE",
"AMS_SAT_GT_TOP_TILE",
"AMS_SAT_GT_BOT_TILE_MY",
"AMS_SAT_GT_TOP_TILE_MY",
] {
for (x, y) in int.find_tiles(&[tkn]) {
let mut col = int.lookup_column_inter(x);
if col.to_idx() != 0 {
col -= 1;
}
let reg = RegId::from_idx(int.lookup_row(y + 1).to_idx() / 48);
let tile = &int.rd.tiles[&Coord {
x: x as u16,
y: y as u16,
}];
if let Some(xy) = extract_site_xy(int.rd, tile, "SYSMON_SAT") {
naming.sysmon_sat_gt.insert((col, reg), xy);
}
let tile = &int.rd.tiles[&Coord {
x: x as u16,
y: (y - 15) as u16,
}];
if let Some(xy) = extract_site_xy(int.rd, tile, "DPLL") {
naming.dpll_gt.insert((col, reg), xy);
}
}
}
}

fn get_grid(
die: DieId,
int: &IntGrid<'_>,
Expand All @@ -429,6 +460,8 @@ fn get_grid(
let mut naming = DieNaming {
hdio: BTreeMap::new(),
sysmon_sat_vnoc: BTreeMap::new(),
sysmon_sat_gt: BTreeMap::new(),
dpll_gt: BTreeMap::new(),
vnoc2: BTreeMap::new(),
};
let (columns, cols_hard) = make_columns(die, int, disabled, &mut naming);
Expand Down Expand Up @@ -480,6 +513,7 @@ fn get_grid(
right,
};
get_vnoc_naming(int, &mut naming, is_vnoc2_scan_offset);
get_gt_naming(int, &mut naming);
let mut die_sll_columns = BTreeSet::new();
for (x, y) in int.find_tiles(&["SLL", "SLL2"]) {
let crd = Coord {
Expand Down
61 changes: 61 additions & 0 deletions prjcombine_versal_rd2db/src/int.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1973,6 +1973,67 @@ pub fn make_int_db(rd: &Part, dev_naming: &DeviceNaming) -> (IntDb, NamingDb) {
xn.bel(bel).extract();
}

for (kind, dpll_kind, tkn, intf_kind, int_dir) in [
(
"SYSMON_SAT.LGT",
"DPLL.LGT",
"AMS_SAT_GT_BOT_TILE_MY",
"INTF.W.TERM.GT",
Dir::E,
),
(
"SYSMON_SAT.LGT",
"DPLL.LGT",
"AMS_SAT_GT_TOP_TILE_MY",
"INTF.W.TERM.GT",
Dir::E,
),
(
"SYSMON_SAT.RGT",
"DPLL.RGT",
"AMS_SAT_GT_BOT_TILE",
"INTF.E.TERM.GT",
Dir::W,
),
(
"SYSMON_SAT.RGT",
"DPLL.RGT",
"AMS_SAT_GT_TOP_TILE",
"INTF.E.TERM.GT",
Dir::W,
),
] {
if let Some(&xy) = rd.tiles_by_kind_name(tkn).iter().next() {
let bel = builder.bel_xy(kind, "SYSMON_SAT", 0, 0);
let intf = builder.ndb.get_node_naming(intf_kind);
let base_xy = builder.delta(xy, 0, -24);
let int_xy = builder.walk_to_int(base_xy, int_dir, true).unwrap();
let intf_xy = builder.delta(int_xy, if int_dir == Dir::E { -1 } else { 1 }, 0);
let mut xn = builder.xnode(kind, kind, xy).num_tiles(48);
for i in 0..48 {
let intf_xy = xn.builder.delta(intf_xy, 0, (i + i / 4) as i32);
xn = xn.ref_single(intf_xy, i, intf)
}
xn.bel(bel).extract();
let bel = builder
.bel_xy(dpll_kind, "DPLL", 0, 0)
.pin_name_only("CLKIN", 1)
.pin_name_only("CLKIN_DESKEW", 1)
.pin_name_only("CLKOUT0", 1)
.pin_name_only("CLKOUT1", 1)
.pin_name_only("CLKOUT2", 1)
.pin_name_only("CLKOUT3", 1)
.pin_name_only("TMUXOUT", 1);
let dpll_xy = builder.delta(xy, 0, -15);
let mut xn = builder.xnode(dpll_kind, dpll_kind, dpll_xy).num_tiles(48);
for i in 0..48 {
let intf_xy = xn.builder.delta(intf_xy, 0, (i + i / 4) as i32);
xn = xn.ref_single(intf_xy, i, intf)
}
xn.bel(bel).extract();
}
}

if let Some(&xy) = rd.tiles_by_kind_name("MISR_TILE").iter().next() {
let bel = builder.bel_xy("MISR", "MISR", 0, 0);
let intf_r = builder.ndb.get_node_naming("INTF.W");
Expand Down
35 changes: 34 additions & 1 deletion prjcombine_versal_rdverify/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -611,6 +611,36 @@ fn verify_dpll_hdio(endev: &ExpandedNamedDevice, vrf: &mut Verifier, bel: &BelCo
}
}

fn verify_dpll_gt(_endev: &ExpandedNamedDevice, vrf: &mut Verifier, bel: &BelContext<'_>) {
vrf.verify_bel(
bel,
"DPLL",
&[
("CLKIN", SitePinDir::In),
("CLKIN_DESKEW", SitePinDir::In),
("CLKOUT0", SitePinDir::Out),
("CLKOUT1", SitePinDir::Out),
("CLKOUT2", SitePinDir::Out),
("CLKOUT3", SitePinDir::Out),
("TMUXOUT", SitePinDir::Out),
],
&[],
);

for pin in ["CLKIN", "CLKIN_DESKEW"] {
vrf.claim_node(&[bel.fwire(pin)]);
// TODO: source instead
vrf.claim_node(&[bel.fwire_far(pin)]);
vrf.claim_pip(bel.crd(), bel.wire(pin), bel.wire_far(pin));
}

for pin in ["CLKOUT0", "CLKOUT1", "CLKOUT2", "CLKOUT3", "TMUXOUT"] {
vrf.claim_node(&[bel.fwire(pin)]);
vrf.claim_node(&[bel.fwire_far(pin)]);
vrf.claim_pip(bel.crd(), bel.wire_far(pin), bel.wire(pin));
}
}

fn verify_rclk_hdio_dpll(vrf: &mut Verifier, bel: &BelContext<'_>) {
let obel_vcc = vrf.find_bel_sibling(bel, "VCC.RCLK_INTF.W");
let obel_hdistr_loc = vrf.find_bel_sibling(bel, "RCLK_HDISTR_LOC.W");
Expand Down Expand Up @@ -936,8 +966,11 @@ fn verify_bel(endev: &ExpandedNamedDevice, vrf: &mut Verifier, bel: &BelContext<
"DFE_CFC_BOT" => verify_hardip(endev, vrf, bel, "DFE_CFC_BOT"),
"DFE_CFC_TOP" => verify_hardip(endev, vrf, bel, "DFE_CFC_TOP"),
"RCLK_DFX_TEST.E" | "RCLK_DFX_TEST.W" => vrf.verify_bel(bel, "RCLK_DFX_TEST", &[], &[]),
"SYSMON_SAT.VNOC" => vrf.verify_bel(bel, "SYSMON_SAT", &[], &[]),
"SYSMON_SAT.VNOC" | "SYSMON_SAT.LGT" | "SYSMON_SAT.RGT" => {
vrf.verify_bel(bel, "SYSMON_SAT", &[], &[])
}
"DPLL.HDIO" => verify_dpll_hdio(endev, vrf, bel),
"DPLL.LGT" | "DPLL.RGT" => verify_dpll_gt(endev, vrf, bel),
"RCLK_HDIO_DPLL" => verify_rclk_hdio_dpll(vrf, bel),
"RCLK_HDIO" => verify_rclk_hdio(endev, vrf, bel),
"RCLK_HB_HDIO" => verify_rclk_hb_hdio(endev, vrf, bel),
Expand Down
4 changes: 1 addition & 3 deletions prjcombine_virtex_bitstream/src/packet.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -705,9 +705,7 @@ impl Iterator for PacketParser<'_> {
Some(Packet::Fdri(src_data[dpos..epos].to_vec()))
}
}
0xd if is_v4 => {
Some(Packet::Axss((0..num).map(get_val).collect()))
}
0xd if is_v4 => Some(Packet::Axss((0..num).map(get_val).collect())),
0x1e => {
self.crc.set(prev_crc);
Some(Packet::Bout(src_data[dpos..epos].to_vec()))
Expand Down

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