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PL clock frequency set to 125MHz
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@bmichel-psee
bmichel-psee committed Nov 8, 2024
1 parent 239e886 commit a3ddd93
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Showing 3 changed files with 37 additions and 42 deletions.
4 changes: 3 additions & 1 deletion CHANGELOG.md
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Original file line number Diff line number Diff line change
@@ -1,13 +1,15 @@
# Prophesee KV260 Project Changelog

## 1.0.0 - (2024-10-21)
## 1.0.0 - (2024-11-08)

### Added

* Script to generate IP simulation projects

### Changed

* PL clock frequency set to 125MHz

* New IPs for kv260 project:
- axis_tkeep_handler v2.0
- event_stream_smart_tracker v2.0
Expand Down
2 changes: 1 addition & 1 deletion projects/kv260/coe/kv260_system_register.coe
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
memory_initialization_radix=16;
memory_initialization_vector=00000039 00010000 15c57eec 0000000C 20241021 00171907 0000000E;
memory_initialization_vector=00000039 00010000 ca211097 0000000C 20241108 00150649 0000000E;
73 changes: 33 additions & 40 deletions projects/kv260/scripts/kv260.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
#
# kv260.tcl: Tcl script for re-creating project 'kv260'
#
# Generated by Vivado on Mon Oct 21 17:19:16 CEST 2024
# Generated by Vivado on Fri Nov 08 15:06:58 CET 2024
# IP Build 3718410 on Thu Dec 8 22:11:41 MST 2022
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
Expand Down Expand Up @@ -726,12 +726,9 @@ proc cr_bd_kv260 { parentCell } {
set axi_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma ]
set_property -dict [list \
CONFIG.c_addr_width {33} \
CONFIG.c_include_mm2s {1} \
CONFIG.c_include_mm2s {0} \
CONFIG.c_include_sg {1} \
CONFIG.c_m_axi_mm2s_data_width {64} \
CONFIG.c_m_axis_mm2s_tdata_width {64} \
CONFIG.c_micro_dma {0} \
CONFIG.c_mm2s_burst_size {8} \
CONFIG.c_s2mm_burst_size {256} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {26} \
Expand All @@ -758,7 +755,7 @@ proc cr_bd_kv260 { parentCell } {
set axi_interconnect_hp0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp0 ]
set_property -dict [list \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {3} \
CONFIG.NUM_SI {2} \
] $axi_interconnect_hp0


Expand All @@ -773,35 +770,40 @@ proc cr_bd_kv260 { parentCell } {
# Create instance: core_clock_0, and set properties
set core_clock_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 core_clock_0 ]
set_property -dict [list \
CONFIG.CLKIN1_JITTER_PS {75.0} \
CONFIG.CLKIN1_JITTER_PS {80.0} \
CONFIG.CLKOUT1_DRIVES {BUFGCE} \
CONFIG.CLKOUT1_JITTER {105.937} \
CONFIG.CLKOUT1_PHASE_ERROR {85.441} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {133.332001} \
CONFIG.CLKOUT1_JITTER {161.298} \
CONFIG.CLKOUT1_PHASE_ERROR {222.308} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKOUT1_USED {true} \
CONFIG.CLKOUT2_DRIVES {BUFGCE} \
CONFIG.CLKOUT2_JITTER {98.191} \
CONFIG.CLKOUT2_PHASE_ERROR {85.441} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200.000} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT2_JITTER {109.242} \
CONFIG.CLKOUT2_PHASE_ERROR {96.948} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {100.000} \
CONFIG.CLKOUT2_USED {false} \
CONFIG.CLKOUT3_DRIVES {BUFGCE} \
CONFIG.CLKOUT4_DRIVES {BUFGCE} \
CONFIG.CLKOUT5_DRIVES {BUFGCE} \
CONFIG.CLKOUT6_DRIVES {BUFGCE} \
CONFIG.CLKOUT7_DRIVES {BUFGCE} \
CONFIG.CLK_OUT1_PORT {core_clk_o} \
CONFIG.CLK_OUT2_PORT {mipi_dphy_clk_o} \
CONFIG.CLK_OUT1_PORT {mipi_dphy_clk_o} \
CONFIG.CLK_OUT2_PORT {clk_out2} \
CONFIG.ENABLE_CLOCK_MONITOR {false} \
CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
CONFIG.MMCM_CLKFBOUT_MULT_F {9.000} \
CONFIG.MMCM_CLKIN1_PERIOD {7.500} \
CONFIG.MMCM_CLKFBOUT_MULT_F {48.000} \
CONFIG.MMCM_CLKIN1_PERIOD {8.000} \
CONFIG.MMCM_CLKIN2_PERIOD {10.000} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {9.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {6} \
CONFIG.MMCM_DIVCLK_DIVIDE {1} \
CONFIG.NUM_OUT_CLKS {2} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {6.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {1} \
CONFIG.MMCM_DIVCLK_DIVIDE {5} \
CONFIG.NUM_OUT_CLKS {1} \
CONFIG.OPTIMIZE_CLOCKING_STRUCTURE_EN {true} \
CONFIG.PRIMITIVE {MMCM} \
CONFIG.PRIM_IN_FREQ {124.998749} \
CONFIG.PRIM_SOURCE {No_buffer} \
CONFIG.RESET_PORT {resetn} \
CONFIG.RESET_TYPE {ACTIVE_LOW} \
CONFIG.USE_LOCKED {false} \
CONFIG.USE_SAFE_CLOCK_STARTUP {true} \
] $core_clock_0

Expand Down Expand Up @@ -1352,12 +1354,10 @@ proc cr_bd_kv260 { parentCell } {
CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {133.332001} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {133.333333} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {124.998749} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {125} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {96.968727} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {99.999001} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {99.999001} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \
Expand Down Expand Up @@ -1506,7 +1506,7 @@ proc cr_bd_kv260 { parentCell } {
CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \
CONFIG.PSU__FPGA_PL0_ENABLE {1} \
CONFIG.PSU__FPGA_PL1_ENABLE {1} \
CONFIG.PSU__FPGA_PL1_ENABLE {0} \
CONFIG.PSU__FPGA_PL2_ENABLE {0} \
CONFIG.PSU__FPGA_PL3_ENABLE {0} \
CONFIG.PSU__FP__POWER__ON {1} \
Expand Down Expand Up @@ -1542,7 +1542,7 @@ proc cr_bd_kv260 { parentCell } {
CONFIG.PSU__GPIO_EMIO_WIDTH {32} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {32} \
CONFIG.PSU__GPIO_EMIO__WIDTH {[91:0]} \
CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
CONFIG.PSU__GPU_PP0__POWER__ON {1} \
CONFIG.PSU__GPU_PP1__POWER__ON {1} \
CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
Expand Down Expand Up @@ -1659,7 +1659,7 @@ proc cr_bd_kv260 { parentCell } {
CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
CONFIG.PSU__NUM_FABRIC_RESETS {4} \
CONFIG.PSU__NUM_FABRIC_RESETS {1} \
CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
Expand All @@ -1685,7 +1685,6 @@ proc cr_bd_kv260 { parentCell } {
CONFIG.PSU__PCIE__VENDOR_ID {} \
CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__PL_CLK0_BUF {TRUE} \
CONFIG.PSU__PL_CLK1_BUF {TRUE} \
CONFIG.PSU__PL__POWER__ON {1} \
CONFIG.PSU__PMU_COHERENCY {0} \
CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
Expand Down Expand Up @@ -1914,10 +1913,9 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000


# Create interface connections
connect_bd_intf_net -intf_net S00_AXI_2 [get_bd_intf_pins axi_dma/M_AXI_MM2S] [get_bd_intf_pins axi_interconnect_hp0/S00_AXI]
connect_bd_intf_net -intf_net S01_AXI_1 [get_bd_intf_pins axi_dma/M_AXI_S2MM] [get_bd_intf_pins axi_interconnect_hp0/S01_AXI]
connect_bd_intf_net -intf_net S02_AXI_1 [get_bd_intf_pins axi_dma/M_AXI_SG] [get_bd_intf_pins axi_interconnect_hp0/S02_AXI]
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins system_register/BRAM_PORTA]
connect_bd_intf_net -intf_net axi_dma_M_AXI_SG [get_bd_intf_pins axi_dma/M_AXI_SG] [get_bd_intf_pins axi_interconnect_hp0/S00_AXI]
connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports gpio_generic] [get_bd_intf_pins axi_gpio_0/GPIO]
connect_bd_intf_net -intf_net axi_interconnect_hp0_M00_AXI [get_bd_intf_pins axi_interconnect_hp0/M00_AXI] [get_bd_intf_pins zynq_processing_system/S_AXI_HPC0_FPD]
connect_bd_intf_net -intf_net axi_interconnect_master_lpd_M00_AXI [get_bd_intf_pins axi_dma/S_AXI_LITE] [get_bd_intf_pins axi_interconnect_master_lpd/M00_AXI]
Expand All @@ -1939,23 +1937,19 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
# Create port connections
connect_bd_net -net PL_PS_IRQ_dout [get_bd_pins PL_PS_IRQ/dout] [get_bd_pins zynq_processing_system/pl_ps_irq0]
connect_bd_net -net aux_reset_in_1 [get_bd_pins ps_system_reset/aux_reset_in] [get_bd_pins ps_system_reset/dcm_locked] [get_bd_pins ps_system_reset/ext_reset_in] [get_bd_pins vcc_constant/dout]
connect_bd_net -net axi_dma_mm2s_introut [get_bd_pins PL_PS_IRQ/In0] [get_bd_pins axi_dma/mm2s_introut]
connect_bd_net -net axi_dma_s2mm_introut [get_bd_pins PL_PS_IRQ/In1] [get_bd_pins axi_dma/s2mm_introut]
connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins PL_PS_IRQ/In2] [get_bd_pins axi_iic_0/iic2intc_irpt]
connect_bd_net -net clk_wiz_0_mipi_dphy_clk_o [get_bd_pins core_clock_0/mipi_dphy_clk_o] [get_bd_pins mipi_csi2_rx_subsyst_0/dphy_clk_200M]
connect_bd_net -net hier_0_pl_resetn0 [get_bd_pins core_clock_0/resetn] [get_bd_pins zynq_processing_system/pl_resetn0]
connect_bd_net -net mipi_csi2_rx_subsyst_0_csirxss_csi_irq [get_bd_pins PL_PS_IRQ/In3] [get_bd_pins mipi_csi2_rx_subsyst_0/csirxss_csi_irq]
connect_bd_net -net pipeline_system_reset_peripheral_reset [get_bd_pins ps_system_reset/peripheral_reset]
connect_bd_net -net ps_system_reset_interconnect_aresetn [get_bd_pins axi_interconnect_hp0/ARESETN] [get_bd_pins axi_interconnect_master_lpd/ARESETN] [get_bd_pins ps_system_reset/interconnect_aresetn]
connect_bd_net -net ps_system_reset_peripheral_reset [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma/axi_resetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_interconnect_hp0/M00_ARESETN] [get_bd_pins axi_interconnect_hp0/S00_ARESETN] [get_bd_pins axi_interconnect_hp0/S01_ARESETN] [get_bd_pins axi_interconnect_hp0/S02_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M00_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M01_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M02_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M03_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M04_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M05_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M06_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M07_ARESETN] [get_bd_pins axi_interconnect_master_lpd/S00_ARESETN] [get_bd_pins axis_tkeep_handler_0/aresetn] [get_bd_pins event_stream_smart_t_0/aresetn] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aresetn] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aresetn] [get_bd_pins ps_host_if_0/aresetn] [get_bd_pins ps_system_reset/peripheral_aresetn]
connect_bd_net -net ps_system_reset_peripheral_reset [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_dma/axi_resetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_interconnect_hp0/M00_ARESETN] [get_bd_pins axi_interconnect_hp0/S00_ARESETN] [get_bd_pins axi_interconnect_hp0/S01_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M00_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M01_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M02_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M03_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M04_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M05_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M06_ARESETN] [get_bd_pins axi_interconnect_master_lpd/M07_ARESETN] [get_bd_pins axi_interconnect_master_lpd/S00_ARESETN] [get_bd_pins axis_tkeep_handler_0/aresetn] [get_bd_pins event_stream_smart_t_0/aresetn] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aresetn] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aresetn] [get_bd_pins ps_host_if_0/aresetn] [get_bd_pins ps_system_reset/peripheral_aresetn]
connect_bd_net -net top_kria_fan_en_b [get_bd_ports fan_en_b] [get_bd_pins xlslice_0/Dout]
connect_bd_net -net zynq_processing_system_hier_emio_ttc0_wave_o [get_bd_pins xlslice_0/Din] [get_bd_pins zynq_processing_system/emio_ttc0_wave_o]
connect_bd_net -net zynq_processing_system_pl_clk0 [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma/m_axi_mm2s_aclk] [get_bd_pins axi_dma/m_axi_s2mm_aclk] [get_bd_pins axi_dma/m_axi_sg_aclk] [get_bd_pins axi_dma/s_axi_lite_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_interconnect_hp0/ACLK] [get_bd_pins axi_interconnect_hp0/M00_ACLK] [get_bd_pins axi_interconnect_hp0/S00_ACLK] [get_bd_pins axi_interconnect_hp0/S01_ACLK] [get_bd_pins axi_interconnect_hp0/S02_ACLK] [get_bd_pins axi_interconnect_master_lpd/ACLK] [get_bd_pins axi_interconnect_master_lpd/M00_ACLK] [get_bd_pins axi_interconnect_master_lpd/M01_ACLK] [get_bd_pins axi_interconnect_master_lpd/M02_ACLK] [get_bd_pins axi_interconnect_master_lpd/M03_ACLK] [get_bd_pins axi_interconnect_master_lpd/M04_ACLK] [get_bd_pins axi_interconnect_master_lpd/M05_ACLK] [get_bd_pins axi_interconnect_master_lpd/M06_ACLK] [get_bd_pins axi_interconnect_master_lpd/M07_ACLK] [get_bd_pins axi_interconnect_master_lpd/S00_ACLK] [get_bd_pins axis_tkeep_handler_0/aclk] [get_bd_pins core_clock_0/clk_in1] [get_bd_pins event_stream_smart_t_0/aclk] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aclk] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aclk] [get_bd_pins ps_host_if_0/aclk] [get_bd_pins ps_system_reset/slowest_sync_clk] [get_bd_pins zynq_processing_system/maxihpm0_fpd_aclk] [get_bd_pins zynq_processing_system/pl_clk0] [get_bd_pins zynq_processing_system/saxihpc0_fpd_aclk]
connect_bd_net -net zynq_processing_system_pl_clk0 [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_dma/m_axi_s2mm_aclk] [get_bd_pins axi_dma/m_axi_sg_aclk] [get_bd_pins axi_dma/s_axi_lite_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_interconnect_hp0/ACLK] [get_bd_pins axi_interconnect_hp0/M00_ACLK] [get_bd_pins axi_interconnect_hp0/S00_ACLK] [get_bd_pins axi_interconnect_hp0/S01_ACLK] [get_bd_pins axi_interconnect_master_lpd/ACLK] [get_bd_pins axi_interconnect_master_lpd/M00_ACLK] [get_bd_pins axi_interconnect_master_lpd/M01_ACLK] [get_bd_pins axi_interconnect_master_lpd/M02_ACLK] [get_bd_pins axi_interconnect_master_lpd/M03_ACLK] [get_bd_pins axi_interconnect_master_lpd/M04_ACLK] [get_bd_pins axi_interconnect_master_lpd/M05_ACLK] [get_bd_pins axi_interconnect_master_lpd/M06_ACLK] [get_bd_pins axi_interconnect_master_lpd/M07_ACLK] [get_bd_pins axi_interconnect_master_lpd/S00_ACLK] [get_bd_pins axis_tkeep_handler_0/aclk] [get_bd_pins core_clock_0/clk_in1] [get_bd_pins event_stream_smart_t_0/aclk] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aclk] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aclk] [get_bd_pins ps_host_if_0/aclk] [get_bd_pins ps_system_reset/slowest_sync_clk] [get_bd_pins zynq_processing_system/maxihpm0_fpd_aclk] [get_bd_pins zynq_processing_system/pl_clk0] [get_bd_pins zynq_processing_system/saxihpc0_fpd_aclk]

# Create address segments
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma/Data_MM2S] [get_bd_addr_segs zynq_processing_system/SAXIGP0/HPC0_DDR_LOW] -force
assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma/Data_MM2S] [get_bd_addr_segs zynq_processing_system/SAXIGP0/HPC0_LPS_OCM] -force
assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma/Data_MM2S] [get_bd_addr_segs zynq_processing_system/SAXIGP0/HPC0_QSPI] -force
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma/Data_S2MM] [get_bd_addr_segs zynq_processing_system/SAXIGP0/HPC0_DDR_LOW] -force
assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma/Data_S2MM] [get_bd_addr_segs zynq_processing_system/SAXIGP0/HPC0_LPS_OCM] -force
assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma/Data_S2MM] [get_bd_addr_segs zynq_processing_system/SAXIGP0/HPC0_QSPI] -force
Expand All @@ -1971,7 +1965,6 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
assign_bd_address -offset 0xA0030000 -range 0x00000080 -target_address_space [get_bd_addr_spaces zynq_processing_system/Data] [get_bd_addr_segs ps_host_if_0/s_axi/Reg] -force

# Exclude Address Segments
exclude_bd_addr_seg -offset 0x000800000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces axi_dma/Data_MM2S] [get_bd_addr_segs zynq_processing_system/SAXIGP0/HPC0_DDR_HIGH]
exclude_bd_addr_seg -offset 0x000800000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces axi_dma/Data_S2MM] [get_bd_addr_segs zynq_processing_system/SAXIGP0/HPC0_DDR_HIGH]
exclude_bd_addr_seg -offset 0x000800000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces axi_dma/Data_SG] [get_bd_addr_segs zynq_processing_system/SAXIGP0/HPC0_DDR_HIGH]
exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_dma/Data_SG] [get_bd_addr_segs zynq_processing_system/SAXIGP0/HPC0_LPS_OCM]
Expand Down

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