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Verilator-specific issue with mixed signed/unsigned arithmetic in
axi_dw_upsizer
#361
opened Dec 19, 2024 by
michael-platzer
"MaxTrans" defined incorrectly in the module documentation
#336
opened Apr 10, 2024 by
deepakmmathew
Pipelines between demux and mux would still cause deadlock in an axi_xbar?
#330
opened Feb 1, 2024 by
lionheart117
Vivado Synthesis Error - [Synth 8-6038] cannot resolve hierarchical name
#313
opened Jul 21, 2023 by
abel-kun
run_vsim.sh: Run simulations in parallel
enhancement
New feature or request
#299
opened Apr 26, 2023 by
colluca
axi_dw_downsizer: AXI Slave BRESP changes in value during BVALID’s wait for BREADY
bug
Something isn't working
#289
opened Mar 28, 2023 by
neildaxiomise
axi_to_mem: Starvation issue: AW channel blocks AR channel forever
bug
Something isn't working
#288
opened Mar 27, 2023 by
neildaxiomise
axi_to_mem
: Comb path from b_ready
to w_ready
bug
#287
opened Mar 13, 2023 by
niwis
Improve AXI cut/multicut.
enhancement
New feature or request
#285
opened Feb 16, 2023 by
thommythomaso
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Updated in the last three days: updated:>2024-12-21.