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Avoid wide signals in sensitivity lists of immediate assertions #269

Avoid wide signals in sensitivity lists of immediate assertions

Avoid wide signals in sensitivity lists of immediate assertions #269

Status Failure
Total duration 52s
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lint.yml

on: pull_request
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1 error and 3 warnings
Verilog Sources
Process completed with exit code 1.
Verilog Sources: src/addr_decode_dync.sv#L149
[verible-verilog-lint] reported by reviewdog 🐶 Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb] Raw Output: message:"Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb]" location:{path:"./src/addr_decode_dync.sv" range:{start:{line:149 column:3}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:149 column:3} end:{line:150}} text:" always_comb begin : proc_check_addr_map\n"}
Verilog Sources: src/multiaddr_decode.sv#L136
[verible-verilog-lint] reported by reviewdog 🐶 Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb] Raw Output: message:"Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb]" location:{path:"./src/multiaddr_decode.sv" range:{start:{line:136 column:3}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:136 column:3} end:{line:137}} text:" always_comb begin : proc_check_addr_map\n"}
Verilog Sources
The following actions use a deprecated Node.js version and will be forced to run on node20: actions/checkout@v3. For more info: https://github.blog/changelog/2024-03-07-github-actions-all-actions-will-run-on-node20-instead-of-node16-by-default/