Merge pull request #14 from pulp-platform/release-1.10

Release 1.10

Bender.yml

@@ -10,7 +10,11 @@ package:
 dependencies:
   tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.1.1 }
 
+export_include_dirs:
+  - include
+
 sources:
+  - src/shift_reg.sv
   - src/fifo_v1.sv
   - src/fifo_v2.sv
   - src/fifo_v3.sv
@@ -20,6 +24,7 @@ sources:
   - src/stream_register.sv
   - src/stream_mux.sv
   - src/stream_demux.sv
+  - src/popcount.sv
   - src/cdc_2phase.sv
   - src/cdc_fifo_2phase.sv
   - src/cdc_fifo_gray.sv
@@ -31,6 +36,7 @@ sources:
   - src/edge_propagator.sv
   - src/lzc.sv
   - src/rrarbiter.sv
+  - src/stream_arbiter_flushable.sv
   - src/stream_arbiter.sv
   - src/sync_wedge.sv
   - src/sync.sv
@@ -39,6 +45,7 @@ sources:
   - src/edge_detect.sv
   - src/serial_deglitch.sv
   - src/counter.sv
+  - src/stream_delay.sv
   - src/mv_filter.sv
 
   - target: simulation

CHANGELOG.md

@@ -4,15 +4,24 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
 and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
 
-## Unreleased
+## 1.10.0 - 2018-12-18
 
+### Added
 - Add `fifo_v3` with generic fill count
 - Add 16 bit LFSR
-- Add ready/valid handshake delayer
+- Add stream delayer
 - Add stream arbiter
+- Add register macros for RTL
+- Add shift register
+
+### Changed
+- Make number of registers of `rstgen_bypass` a parameter.
 
 ### Fixed
 - Fix `valid_i` and `grant_i` guarantees in `generic_fifo` for backward compatibility.
+- LZC: Synthesis of streaming operators in ternary operators
+- Add missing entry for `popcount` to `Bender.yml`.
+- Add default values for parameters to improve compatibility with Synopsys DC and Vivado.
 
 ## 1.9.0 - 2018-11-02
 

README.md

@@ -55,15 +55,15 @@ Please note that cells with status *deprecated* are not to be used for new desig
 | `gray_to_binary`           | Gray code to binary converter                                                | active       |
 | `lzc`                      | Leading/trailing-zero counter                                                | active       |
 | `onehot_to_bin`            | One-hot to binary converter                                                  | active       |
-| `pipe_reg_simple`          | Pipeline register for arbitrary types                                        | active       |
+| `shift_reg`                | Shift register for arbitrary types                                           | active       |
 | `rrarbiter`                | Round-robin arbiter for req/ack interface with look-ahead                    | active       |
 | `spill_register`           | Register with ready/valid interface to cut all combinational interface paths | active       |
 | `stream_arbiter`           | Round-robin arbiter for ready/valid stream interface                         | active       |
 | `stream_arbiter_flushable` | Round-robin arbiter for ready/valid stream interface and flush functionality | active       |
 | `stream_demux`             | Ready/valid interface demultiplexer                                          | active       |
 | `stream_mux`               | Ready/valid interface multiplexer                                            | active       |
 | `stream_register`          | Register with ready/valid interface                                          | active       |
-| `ready_valid_delay`        | Randomize or delay ready/valid interface                                     | active       |
+| `stream_delay`             | Randomize or delay ready/valid interface                                     | active       |
 | `popcount`                 | Combinatorial popcount (hamming weight)                                      | active       |
 
 ### Data Structures
@@ -83,9 +83,9 @@ Please note that cells with status *deprecated* are not to be used for new desig
 
 This repository currently contains the following header files.
 
-### Register Header
+### RTL Register Macros
 
-The register header file `register_defines.svh` contains macros that expand to descriptions of registers.
+The header file `registers.svh` contains macros that expand to descriptions of registers.
 To avoid misuse of `always_ff` blocks, only the following macros shall be used to describe sequential behavior.
 The use of linter rules that flag explicit uses of `always_ff` in source code is encouraged.
 

header/register_defines.svh → include/common_cells/registers.svh

@@ -1,6 +1,17 @@
+// Copyright 2018 ETH Zurich and University of Bologna.
+//
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
 // Common register defines for RTL designs
-`ifndef REGISTER_DEFINES_H_
-`define REGISTER_DEFINES_H_
+`ifndef COMMON_CELLS_REGISTERS_SVH_
+`define COMMON_CELLS_REGISTERS_SVH_
 
 // Abridged Summary of available FF macros:
 // `FF:      asynchronous active-low reset (implicit clock and reset)

src/deprecated/find_first_one.sv

@@ -1,16 +1,13 @@
-// Copyright (c) 2018 ETH Zurich, University of Bologna
-// All rights reserved.
+// Copyright 2018 ETH Zurich and University of Bologna.
 //
-// This code is under development and not yet released to the public.
-// Until it is released, the code is under the copyright of ETH Zurich and
-// the University of Bologna, and may contain confidential and/or unpublished
-// work. Any reuse/redistribution is strictly forbidden without written
-// permission from ETH Zurich.
-//
-// Bug fixes and contributions will eventually be released under the
-// SolderPad open hardware license in the context of the PULP platform
-// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
-// University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
 
 // Deprecated, use lzc unit instead.
 

src/lzc.sv

@@ -41,7 +41,11 @@ module lzc #(
   logic [WIDTH-1:0] in_tmp;
 
   // reverse vector if required
-  assign in_tmp = MODE ? {<<{in_i}} : in_i;
+  always_comb begin : flip_vector
+    in_tmp = in_i;
+    if (MODE)
+      in_tmp = {<< {in_i}};
+  end
 
   for (genvar j = 0; j < WIDTH; j++) begin : g_index_lut
     assign index_lut[j] = j;

src/popcount.sv

@@ -1,16 +1,3 @@
-//-----------------------------------------------------------------------------
-// Title         : Popcount
-//-----------------------------------------------------------------------------
-// File          : popcount.sv
-// Author        : Manuel Eggimann  <[email protected]>
-// Created       : 01.11.2018
-//-----------------------------------------------------------------------------
-// Description :
-// This module calculates the hamming weight (number of ones) in its input vector using a
-// balanced binary adder tree. Recursive instantiation is used to build the tree.
-// Any unsigned INPUT_WIDTH larger or equal 2 is legal. The module pads the signal internally
-// to the next power of two. The output result width is ceil(log2(INPUT_WIDTH))+1.
-//-----------------------------------------------------------------------------
 // Copyright (C) 2013-2018 ETH Zurich, University of Bologna
 // Copyright and related rights are licensed under the Solderpad Hardware
 // License, Version 0.51 (the "License"); you may not use this file except in
@@ -20,7 +7,14 @@
 // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
 // CONDITIONS OF ANY KIND, either express or implied. See the License for the
 // specific language governing permissions and limitations under the License.
-//-----------------------------------------------------------------------------
+
+// Author: Manuel Eggimann <[email protected]>
+
+// Description: This module calculates the hamming weight (number of ones) in
+// its input vector using a balanced binary adder tree. Recursive instantiation
+// is used to build the tree.  Any unsigned INPUT_WIDTH larger or equal 2 is
+// legal.  The module pads the signal internally to the next power of two.  The
+// output result width is ceil(log2(INPUT_WIDTH))+1.
 
 module popcount #(
     parameter int unsigned INPUT_WIDTH = 256,

src/pipe_reg_simple.sv → src/shift_reg.sv

@@ -13,7 +13,7 @@
 //
 // Description: Simple shift register for arbitrary depth and types
 
-module pipe_reg_simple #(
+module shift_reg #(
     parameter type dtype         = logic,
     parameter int unsigned Depth = 1
 )(

src/spill_register.sv

@@ -1,16 +1,13 @@
-// Copyright (c) 2018 ETH Zurich, University of Bologna
-// All rights reserved.
+// Copyright 2018 ETH Zurich and University of Bologna.
 //
-// This code is under development and not yet released to the public.
-// Until it is released, the code is under the copyright of ETH Zurich and
-// the University of Bologna, and may contain confidential and/or unpublished
-// work. Any reuse/redistribution is strictly forbidden without written
-// permission from ETH Zurich.
-//
-// Bug fixes and contributions will eventually be released under the
-// SolderPad open hardware license in the context of the PULP platform
-// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
-// University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
 //
 // Fabian Schuiki <[email protected]>
 

src/stream_arbiter.sv

@@ -14,8 +14,8 @@
 // arbitration scheme is round-robin with "look ahead", see the `rrarbiter` for details.
 
 module stream_arbiter #(
-    parameter type      DATA_T = logic,  // Vivado requires a default value for type parameters.
-    parameter integer   N_INP
+    parameter type      DATA_T = logic,   // Vivado requires a default value for type parameters.
+    parameter integer   N_INP = -1        // Synopsys DC requires a default value for parameters.
 ) (
     input  logic              clk_i,
     input  logic              rst_ni,
@@ -29,27 +29,19 @@ module stream_arbiter #(
     input  logic              oup_ready_i
 );
 
-  logic [$clog2(N_INP)-1:0] idx;
-
-  rrarbiter #(
-    .NUM_REQ  (N_INP),
-    // Lock arbitration decision once the output is valid and until the handshake happens.
-    .LOCK_IN  (1)
-  ) i_arbiter (
-    .clk_i    (clk_i),
-    .rst_ni   (rst_ni),
-    .flush_i  (1'b0),
-    .en_i     (oup_ready_i),
-    .req_i    (inp_valid_i),
-    .ack_o    (inp_ready_o),
-    // The `vld_o` port of `rrarbiter` combinatorially depends on `en_i`.  In the stream protocol,
-    // a valid may not depend on a ready, so we drive `oup_valid_o` from the `inp_valid_i`s in (1)
-    // and leave `vld_o` unconnected.
-    .vld_o    (),
-    .idx_o    (idx)
+  stream_arbiter_flushable #(
+    .DATA_T (DATA_T),
+    .N_INP  (N_INP)
+  ) i_arb (
+    .clk_i        (clk_i),
+    .rst_ni       (rst_ni),
+    .flush_i      (1'b0),
+    .inp_data_i   (inp_data_i),
+    .inp_valid_i  (inp_valid_i),
+    .inp_ready_o  (inp_ready_o),
+    .oup_data_o   (oup_data_o),
+    .oup_valid_o  (oup_valid_o),
+    .oup_ready_i  (oup_ready_i)
   );
 
-  assign oup_valid_o = (|inp_valid_i); // (1), see reference above.
-  assign oup_data_o = inp_data_i[idx];
-
 endmodule

src/stream_arbiter_flushable.sv

@@ -14,8 +14,8 @@
 // arbitration scheme is round-robin with "look ahead", see the `rrarbiter` for details.
 
 module stream_arbiter_flushable #(
-    parameter type      DATA_T = logic,  // Vivado requires a default value for type parameters.
-    parameter integer   N_INP
+    parameter type      DATA_T = logic,   // Vivado requires a default value for type parameters.
+    parameter integer   N_INP = -1        // Synopsys DC requires a default value for parameters.
 ) (
     input  logic              clk_i,
     input  logic              rst_ni,

src/ready_valid_delay.sv → src/stream_delay.sv

@@ -11,7 +11,7 @@
 // Author: Florian Zaruba, [email protected]
 // Description: Delay (or randomize) AXI-like handshaking
 
-module ready_valid_delay #(
+module stream_delay #(
     parameter bit   StallRandom = 0,
     parameter int   FixedDelay  = 1,
     parameter type  payload_t  = logic

src/stream_mux.sv

@@ -13,7 +13,7 @@
 
 module stream_mux #(
   parameter type DATA_T = logic,  // Vivado requires a default value for type parameters.
-  parameter integer N_INP,
+  parameter integer N_INP = 0,    // Synopsys DC requires a default value for value parameters.
   /// Dependent parameters, DO NOT OVERRIDE!
   localparam integer LOG_N_INP = $clog2(N_INP)
 ) (
@@ -35,4 +35,12 @@ module stream_mux #(
   assign oup_data_o   = inp_data_i[inp_sel_i];
   assign oup_valid_o  = inp_valid_i[inp_sel_i];
 
+// pragma translate_off
+`ifndef VERILATOR
+  initial begin: p_assertions
+    assert (N_INP >= 1) else $fatal ("The number of inputs must be at least 1!");
+  end
+`endif
+// pragma translate_on
+
 endmodule

src/stream_register.sv

@@ -12,7 +12,7 @@
 /// This register does not cut combinatorial paths on all control signals; if you need a complete
 /// cut, use the `spill_register`.
 module stream_register #(
-    parameter type T
+    parameter type T = logic  // Vivado requires a default value for type parameters.
 ) (
     input  logic    clk_i,          // Clock
     input  logic    rst_ni,         // Asynchronous active-low reset

src_files.yml

@@ -1,5 +1,6 @@
 common_cells_all:
   files:
+    - src/shift_reg.sv
     - src/fifo_v1.sv
     - src/fifo_v2.sv
     - src/fifo_v3.sv
@@ -25,6 +26,7 @@ common_cells_all:
     - src/edge_detect.sv
     - src/serial_deglitch.sv
     - src/counter.sv
+    - src/stream_delay.sv
     - src/mv_filter.sv
     - src/popcount.sv