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Avoid wide signals in sensitivity lists of immediate assertions
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Verilator has decent support for various types of assertions by now but
dislikes wide signals (e.g., wider than 64 bits) in sensitivity lists.
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@michael-platzer
michael-platzer committed Sep 30, 2024
1 parent 10dac0f commit a0525f7
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Showing 2 changed files with 2 additions and 2 deletions.
2 changes: 1 addition & 1 deletion src/addr_decode_dync.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -146,7 +146,7 @@ module addr_decode_dync #(
// check_start: Enforces a smaller start than end address.
// check_idx: Enforces a valid index in the rule.
// check_overlap: Warns if there are overlapping address regions.
always @(addr_map_i or config_ongoing_i) #0 begin : proc_check_addr_map
always @* begin : proc_check_addr_map

Check warning on line 149 in src/addr_decode_dync.sv

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[verible-verilog-lint] reported by reviewdog 🐶
Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb]

Raw Output:
message:"Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb]"  location:{path:"./src/addr_decode_dync.sv"  range:{start:{line:149  column:3}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:149  column:3}  end:{line:150}}  text:"  always_comb begin : proc_check_addr_map\n"}
if (!$isunknown(addr_map_i) && ~config_ongoing_i) begin
for (int unsigned i = 0; i < NoRules; i++) begin
check_start : assume (Napot || addr_map_i[i].start_addr < addr_map_i[i].end_addr ||
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2 changes: 1 addition & 1 deletion src/multiaddr_decode.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -133,7 +133,7 @@ module multiaddr_decode #(

// These following assumptions check the validity of the address map.
// check_idx: Enforces a valid index in the rule.
always @(addr_map_i) #0 begin : proc_check_addr_map
always @* begin : proc_check_addr_map

Check warning on line 136 in src/multiaddr_decode.sv

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GitHub Actions / Verilog Sources 

[verible-verilog-lint] reported by reviewdog 🐶
Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb]

Raw Output:
message:"Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb]"  location:{path:"./src/multiaddr_decode.sv"  range:{start:{line:136  column:3}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:136  column:3}  end:{line:137}}  text:"  always_comb begin : proc_check_addr_map\n"}
if (!$isunknown(addr_map_i)) begin
for (int unsigned i = 0; i < NoRules; i++) begin
// check the SLV ids
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