Add flushable_spill_register (#119)

* add flushable spill_register

* make spill_register a wrapper of spill_register_flushable

* fix dependency ordering of Bender.yml/src_files.yml

* add sram to src_files (deprecated)

* Adjust wrapper

Co-authored-by: Georg Rutishauser <[email protected]>

Bender.yml

@@ -44,7 +44,7 @@ sources:
   - src/rstgen_bypass.sv
   - src/serial_deglitch.sv
   - src/shift_reg.sv
-  - src/spill_register.sv
+  - src/spill_register_flushable.sv
   - src/stream_demux.sv
   - src/stream_filter.sv
   - src/stream_fork.sv
@@ -59,27 +59,28 @@ sources:
   - src/addr_decode.sv
   - src/cb_filter.sv
   - src/cdc_fifo_2phase.sv
-  - src/cdc_fifo_gray.sv
   - src/counter.sv
   - src/ecc_decode.sv
   - src/ecc_encode.sv
   - src/edge_detect.sv
   - src/lzc.sv
   - src/max_counter.sv
   - src/rstgen.sv
+  - src/spill_register.sv
   - src/stream_delay.sv
   - src/stream_fifo.sv
   - src/stream_fork_dynamic.sv
-  - src/stream_xbar.sv
   # Level 2
+  - src/cdc_fifo_gray.sv
   - src/fall_through_register.sv
   - src/id_queue.sv
   - src/stream_to_mem.sv
   - src/stream_arbiter_flushable.sv
-  - src/stream_omega_net.sv
   - src/stream_register.sv
+  - src/stream_xbar.sv
   # Level 3
   - src/stream_arbiter.sv
+  - src/stream_omega_net.sv
 
   - target: simulation
     files:

CHANGELOG.md

@@ -8,6 +8,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 ### Changed
 - `registers.svh`: Merge explicit and implicit register variants into `` `FF `` and `` `FFL `` macros
 
+## 1.22.0 - 2021-06-09
+### Added
+- Add `spill_register_flushable`
+
+### Changed
+- `rr_arb_tree`: Allow flushing locked decision
+- Improved `verific` compatibility
+
 ## 1.21.0 - 2021-01-28
 ### Changed
 - Remove `timeprecision/timeunit` arguments