v1.27.0
1.27.0 - 2022-12-01
Added
- Add
mem_to_banks
: split memory access over multiple parallel banks. Moved from theAXI4+ATOP
axi_to_mem
module. - Add
read
: dummy module that prevents a signal from being removed during synthesis
Changed
stream_fifo_optimal_wrap
: Remove assertsfall_through_register
: Update fifo tofifo_v3
Fixed
- FuseSoC: Add
assertions.svh