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frontend: fix obi_demux and addr decode
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Lucia Luzi committed Feb 4, 2025
1 parent 32af128 commit fa479e5
Showing 1 changed file with 32 additions and 30 deletions.
62 changes: 32 additions & 30 deletions src/frontend/inst64/idma_inst64_top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,7 @@ module idma_inst64_top #(
localparam int unsigned RepWidth = 32'd32;
localparam int unsigned NumDim = 32'd2;
localparam int unsigned BufferDepth = 32'd64;
localparam int unsigned NumRules = 32'd4;
localparam int unsigned NumRules = 32'd5;

// derived constants and types
localparam int unsigned StrbWidth = AxiDataWidth / 32'd8;
Expand Down Expand Up @@ -149,6 +149,7 @@ module idma_inst64_top #(
obi_req_t [NumChannels-1:0] obi_read_req, obi_write_req;
obi_res_t [NumChannels-1:0] obi_read_rsp, obi_write_rsp;
logic [NumChannels-1:0] obi_we_q, obi_we_d;

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[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L151

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/frontend/inst64/idma_inst64_top.sv" range:{start:{line:151 column:56}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:151 column:56} end:{line:152}} text:"    logic     [NumChannels-1:0] obi_we_q,     obi_we_d;\n"}
logic obi_req_o_rready;

// backend signals
idma_req_t [NumChannels-1:0] idma_req;
Expand Down Expand Up @@ -194,12 +195,12 @@ module idma_inst64_top #(
logic acc_res_ready;

// decoder signals
logic [NumRules-1:0] idx_src;
logic idx_src_valid;
logic idx_src_error;
logic [NumRules-1:0] idx_dst;
logic idx_dst_valid;
logic idx_dst_error;
logic [$clog2(NumRules)-1:0] idx_src;
logic idx_src_valid;
logic idx_src_error;
logic [$clog2(NumRules)-1:0] idx_dst;
logic idx_dst_valid;
logic idx_dst_error;

//--------------------------------------
// Backend instantiation
Expand Down Expand Up @@ -310,13 +311,14 @@ module idma_inst64_top #(

stream_demux #(
.N_OUP ( 32'd2 )
) i_stream_demux (
) i_obi_rw_demux (
.inp_valid_i ( obi_res_i[c].rvalid ),
.inp_ready_o ( obi_req_o[c].rready ),
.oup_sel_i ( obi_we_q[c] ),
.inp_ready_o ( obi_req_o_rready ),
.oup_sel_i ( obi_we_d[c] ),
.oup_valid_o ( {obi_write_rsp[c].rvalid , obi_read_rsp[c].rvalid } ),
.oup_ready_i ( {obi_write_req[c].rready , obi_read_req[c].rready } )
);
assign obi_req_o[c].rready = obi_req_o_rready;


assign busy_o[c] = (|idma_busy[c]) | idma_nd_busy[c];
Expand Down Expand Up @@ -433,33 +435,33 @@ module idma_inst64_top #(

// Address Decode
addr_decode #(
.NoIndices ( 32'd2 ),
.NoRules ( 32'd2 ),
.addr_t ( addr_t ),
.rule_t ( addr_rule_t )
.NoIndices ( $clog2(NumRules) ),
.NoRules ( NumRules ),
.addr_t ( addr_t ),
.rule_t ( addr_rule_t )
) i_idma_src_decode (
.addr_i ( idma_fe_req_d.burst_req.src_addr[AxiAddrWidth-1:0] ),
.addr_map_i ( addr_map_i ),
.idx_o ( idx_src ),
.dec_valid_o ( idx_src_valid ),
.dec_error_o ( idx_src_error ),
.en_default_idx_i ( 1'b1 ),
.default_idx_i ( 32'd4 )
.addr_map_i ( addr_map_i ),
.idx_o ( idx_src ),
.dec_valid_o ( idx_src_valid ),
.dec_error_o ( idx_src_error ),
.en_default_idx_i ( 1'b1 ),
.default_idx_i ( 32'd4 )
);
// address decoder for destination address
addr_decode #(
.NoIndices ( 32'd2 ),
.addr_t ( addr_t ),
.NoRules ( 32'd2 ),
.rule_t ( addr_rule_t )
.NoIndices ( $clog2(NumRules) ),
.addr_t ( addr_t ),
.NoRules ( NumRules ),
.rule_t ( addr_rule_t )
) i_idma_dst_decode (
.addr_i ( idma_fe_req_d.burst_req.dst_addr[AxiAddrWidth-1:0] ),
.addr_map_i ( addr_map_i ),
.idx_o ( idx_dst ),
.dec_valid_o ( idx_dst_valid ),
.dec_error_o ( idx_dst_error ),
.en_default_idx_i ( 1'b1 ),
.default_idx_i ( 32'd4 )
.addr_map_i ( addr_map_i ),
.idx_o ( idx_dst ),
.dec_valid_o ( idx_dst_valid ),
.dec_error_o ( idx_dst_error ),
.en_default_idx_i ( 1'b1 ),
.default_idx_i ( 32'd4 )
);


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