Better scm implementation of X buffer

pulp-platform · Jan 24, 2025 · 6c5c58e · 6c5c58e
1 parent ca1da76
commit 6c5c58e
Showing 4 changed files with 199 additions and 39 deletions.
diff --git a/Bender.yml b/Bender.yml
@@ -32,15 +32,19 @@ sources:
     - rtl/redmule_castin.sv
     - rtl/redmule_castout.sv
     - rtl/redmule_streamer.sv
-    - rtl/redmule_x_buffer.sv
-    - rtl/redmule_w_buffer.sv
+    - rtl/x_buffer/redmule_x_buffer.sv
+    - rtl/x_buffer/redmule_x_pad_scm.sv      
+    - rtl/x_buffer/redmule_x_buffer_scm.sv
+    - rtl/redmule_w_buffer.sv      
     - rtl/redmule_z_buffer.sv
     - rtl/redmule_fma.sv
     - rtl/redmule_noncomp.sv
     - rtl/redmule_ce.sv
     - rtl/redmule_row.sv
     - rtl/redmule_engine.sv
     - rtl/redmule_top.sv
+    - rtl/redmule_fifo_scm.sv
+    - rtl/redmule_memory_scheduler.sv
 
     - target: redmule_hwpe
       files:

diff --git a/rtl/redmule_x_buffer.sv → rtl/x_buffer/redmule_x_buffer.sv b/rtl/redmule_x_buffer.sv → rtl/x_buffer/redmule_x_buffer.sv
@@ -43,12 +43,15 @@ logic [H-1:0][W-1:0][BITW-1:0]  x_buffer_q;
 logic [$clog2(TOT_DEPTH)-1:0]   pad_r_addr_d, pad_r_addr_q;
 logic                           buf_r_addr, buf_w_addr;
 
+logic pad_read_en,
+      buf_read_en;
+
+logic [$clog2(TOT_DEPTH)-1:0] pad_read_addr;
+
 logic h_shift_del;
 
 logic first_block, refilling;
 
-logic pad_read_enable;
-
 always_ff @(posedge clk_i or negedge rst_ni) begin : first_block_register
   if(~rst_ni) begin
     first_block <= '0;
@@ -82,41 +85,41 @@ always_ff @(posedge clk_i or negedge rst_ni) begin : h_shift_delay
   end
 end
 
-for (genvar w = 0; w < W; w++) begin : gen_x_pad
-  redmule_fifo_scm #(
-    .ADDR_WIDTH ( $clog2(TOT_DEPTH) ),
-    .DATA_WIDTH ( BITW              ),
-    .N_INPUTS   ( TOT_DEPTH         ) 
-  ) (
-    .clk          ( clk_i                                                                          ),
-    .rst_n        ( rst_ni                                                                         ),
-    .ReadEnable   ( ctrl_i.h_shift && ~refilling || h_shift_del && first_block || ctrl_i.pad_setup ),
-    .ReadAddr     ( ctrl_i.dequant ? next_wrow_i : ctrl_i.pad_setup ? '0 : pad_r_addr_d            ),
-    .ReadData     ( x_pad_q[w]                                                                     ),
-    .WriteEnable  ( w_index == w && ctrl_i.load                                                    ),
-    .WriteAddr    ( '0                                                                             ),
-    .WriteData    ( x_buffer_i                                                                     )
-  );
-end
+assign pad_read_en   = ctrl_i.h_shift && ~refilling || h_shift_del && first_block || ctrl_i.pad_setup;
+assign pad_read_addr = ctrl_i.dequant ? next_wrow_i : ctrl_i.pad_setup ? '0 : pad_r_addr_d;
 
-assign pad_read_enable = ctrl_i.h_shift && ~refilling || h_shift_del && first_block || ctrl_i.pad_setup;
+redmule_x_pad_scm #(
+  .WORD_SIZE ( BITW      ),
+  .ROWS      ( W         ),
+  .COLS      ( TOT_DEPTH )     
+) i_x_pad (
+  .clk_i        ( clk_i         ),
+  .rst_ni       ( rst_ni        ),
+  .write_en_i   ( ctrl_i.load   ),
+  .write_addr_i ( w_index       ),
+  .wdata_i      ( x_buffer_i    ),
+  .read_en_i    ( pad_read_en   ),
+  .read_addr_i  ( pad_read_addr ),  
+  .rdata_o      ( x_pad_q       )      
+);
 
-for (genvar h = 0; h < H; h++) begin : gen_x_buf
-  redmule_fifo_scm #(
-    .ADDR_WIDTH ( 1       ),
-    .DATA_WIDTH ( W*BITW  ),
-    .N_INPUTS   ( 1       ) 
-  ) (
-    .clk          ( clk_i                                                                           ),
-    .rst_n        ( rst_ni                                                                          ),
-    .ReadEnable   ( ctrl_i.h_shift && h_index_r == h                                                ),
-    .ReadAddr     ( buf_r_addr                                                                      ),
-    .ReadData     ( x_buffer_q[h]                                                                   ),
-    .WriteEnable  ( (ctrl_i.h_shift && ~refilling || h_shift_del && first_block) && h_index_w == h  ),
-    .WriteAddr    ( buf_w_addr                                                                      ),
-    .WriteData    ( x_pad_q                                                                         )
-  );
-end
+assign buf_write_en = ctrl_i.h_shift && ~refilling || h_shift_del && first_block;
+
+redmule_x_buffer_scm #(
+  .WORD_SIZE ( BITW ),
+  .WIDTH     ( W    ),
+  .HEIGHT    ( 2    ),
+  .N_OUTPUTS ( H    )
+) i_x_buf (
+  .clk_i        ( clk_i                   ),
+  .rst_ni       ( rst_ni                  ),
+  .write_en_i   ( buf_write_en            ),
+  .write_addr_i ( {buf_w_addr, h_index_w} ),
+  .wdata_i      ( x_pad_q                 ),
+  .read_en_i    ( ctrl_i.h_shift          ),
+  .read_addr_i  ( {buf_r_addr, h_index_r} ),
+  .rdata_o      ( x_buffer_q              )      
+);
 
 assign buf_w_addr = (first_block && pad_r_addr_q < H) ? buf_r_addr : ~buf_r_addr;
 assign h_index_w  = first_block ? 2*h_index_r - h_shift_del : h_index_r;
@@ -127,7 +130,7 @@ always_ff @(posedge clk_i or negedge rst_ni) begin : x_pad_read_pointer
   end else begin
     if (clear_i || rst_h_shift)
       pad_r_addr_q <= '0;
-    else if (ctrl_i.h_shift && ~refilling || h_shift_del && first_block /*|| ctrl_i.pad_setup*/)
+    else if (buf_write_en)
       pad_r_addr_q <= pad_r_addr_d;
   end
 end
@@ -243,7 +246,7 @@ always_ff @(posedge clk_i or negedge rst_ni) begin : h_shift_counter
   end
 end
 
-assign next_wrow_ready_o = pad_read_enable;
+assign next_wrow_ready_o = pad_read_en;
 
 // Output assignment
 // verilog_lint: waive-start generate-label

diff --git a/rtl/x_buffer/redmule_x_buffer_scm.sv b/rtl/x_buffer/redmule_x_buffer_scm.sv
@@ -0,0 +1,82 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Andrea Belano <andrea.belano2@unibo.it>
+//
+
+module redmule_x_buffer_scm #(
+  parameter int unsigned WORD_SIZE = 32,
+  parameter int unsigned WIDTH     = 1 ,
+  parameter int unsigned HEIGHT    = 2 ,
+  parameter int unsigned N_OUTPUTS = 1 
+) (
+  input  logic                                           clk_i        ,
+  input  logic                                           rst_ni       ,
+  input  logic                                           write_en_i   ,
+  input  logic [$clog2(N_OUTPUTS)+$clog2(HEIGHT)-1:0]    write_addr_i ,
+  input  logic [WIDTH-1:0][WORD_SIZE-1:0]                wdata_i      ,
+  input  logic                                           read_en_i    ,
+  input  logic [$clog2(N_OUTPUTS)+$clog2(HEIGHT)-1:0]    read_addr_i  ,  
+  output logic [N_OUTPUTS-1:0][WIDTH-1:0][WORD_SIZE-1:0] rdata_o      
+);
+  logic [HEIGHT-1:0][N_OUTPUTS-1:0][WIDTH-1:0][WORD_SIZE-1:0] buffer_q; 
+  logic [WIDTH-1:0][WORD_SIZE-1:0]                            wdata_q;
+  logic [N_OUTPUTS-1:0][$clog2(HEIGHT)-1:0]                   read_addr_q;
+
+  logic [$clog2(N_OUTPUTS)-1:0]                               row_w_addr;
+  logic [$clog2(HEIGHT)-1:0]                                  slot_w_addr;
+
+  logic [HEIGHT-1:0][N_OUTPUTS-1:0]                           clk_w;
+
+  for (genvar o = 0; o < N_OUTPUTS; o++) begin : gen_read_addr_registers
+    always_ff @(posedge clk_i or negedge rst_ni) begin : sample_raddr
+      if(~rst_ni) begin
+        read_addr_q[o] <= '0;
+      end else begin
+        if (read_en_i && read_addr_i[$clog2(N_OUTPUTS)-1:0] == o) begin
+          read_addr_q[o] <= read_addr_i[$clog2(N_OUTPUTS)+:$clog2(HEIGHT)];
+        end
+      end
+    end
+  end
+
+  for (genvar o = 0; o < N_OUTPUTS; o++) begin : output_assignment
+    assign rdata_o[o] = buffer_q[read_addr_q[o]][o];
+  end
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : sample_wdata
+    if(~rst_ni) begin
+      wdata_q <= '0;
+    end else begin
+      if (write_en_i) begin
+        wdata_q <= wdata_i;
+      end
+    end
+  end
+
+  assign row_w_addr  = write_addr_i[$clog2(N_OUTPUTS)-1:0];
+  assign slot_w_addr = write_addr_i[$clog2(N_OUTPUTS)+:$clog2(HEIGHT)];
+
+  for (genvar h = 0; h < HEIGHT; h++) begin : gen_slots_cg
+    for (genvar o = 0; o < N_OUTPUTS; o++) begin : gen_rows_cg
+      tc_clk_gating i_row_cg (
+        .clk_i     ( clk_i                                             ),
+        .en_i      ( row_w_addr == o && slot_w_addr == h && write_en_i ),
+        .test_en_i ( '0                                                ),
+        .clk_o     ( clk_w[h][o]                                       )
+      );
+    end
+  end
+
+  for (genvar h = 0; h < HEIGHT; h++) begin : gen_slots
+    for (genvar o = 0; o < N_OUTPUTS; o++) begin : gen_rows
+      always_latch begin : latch_wdata
+        if (clk_w[h][o]) begin
+          buffer_q[h][o] = wdata_q;
+        end
+      end
+    end
+  end
+
+endmodule
diff --git a/rtl/x_buffer/redmule_x_pad_scm.sv b/rtl/x_buffer/redmule_x_pad_scm.sv
@@ -0,0 +1,71 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Andrea Belano <andrea.belano2@unibo.it>
+//
+
+module redmule_x_pad_scm #(
+  parameter int unsigned WORD_SIZE = 32,
+  parameter int unsigned ROWS      = 1 ,
+  parameter int unsigned COLS      = 1 
+) (
+  input  logic                           clk_i        ,
+  input  logic                           rst_ni       ,
+  input  logic                           write_en_i   ,
+  input  logic [$clog2(ROWS)-1:0]        write_addr_i ,
+  input  logic [COLS-1:0][WORD_SIZE-1:0] wdata_i      ,
+  input  logic                           read_en_i    ,
+  input  logic [$clog2(COLS)-1:0]        read_addr_i  ,  
+  output logic [ROWS-1:0][WORD_SIZE-1:0] rdata_o      
+);
+  logic [ROWS-1:0][COLS-1:0][WORD_SIZE-1:0] buffer_q; 
+  logic [COLS-1:0][WORD_SIZE-1:0]           wdata_q;
+  logic [$clog2(COLS)-1:0]                  read_addr_q;
+
+  logic [ROWS-1:0]                          clk_w;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : sample_raddr
+    if(~rst_ni) begin
+      read_addr_q <= '0;
+    end else begin
+      if (read_en_i) begin
+        read_addr_q <= read_addr_i;
+      end
+    end
+  end
+
+  for (genvar r = 0; r < ROWS; r++) begin : output_assignment
+    assign rdata_o[r] = buffer_q[r][read_addr_q];
+  end
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : sample_wdata
+    if(~rst_ni) begin
+      wdata_q <= '0;
+    end else begin
+      if (write_en_i) begin
+        wdata_q <= wdata_i;
+      end
+    end
+  end
+
+  for (genvar r = 0; r < ROWS; r++) begin : gen_write_clock_gates
+    tc_clk_gating i_rows_cg (
+      .clk_i     ( clk_i                           ),
+      .en_i      ( write_addr_i == r && write_en_i ),
+      .test_en_i ( '0                              ),
+      .clk_o     ( clk_w[r]                        )
+    );
+  end
+
+  for (genvar r = 0; r < ROWS; r++) begin : gen_rows
+    for (genvar c = 0; c < COLS; c++) begin : gen_cols
+      always_latch begin : latch_wdata
+        if (clk_w[r]) begin
+          buffer_q[r][c] = wdata_q[c];
+        end
+      end
+    end
+  end
+
+endmodule