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Merge pull request #33 from pulp-platform/yt/verilator
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Add Verilator simulation support and fully open-source CI flow.
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yvantor authored Nov 10, 2024
2 parents 60a6efc + 699505f commit 93a95ce
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92 changes: 92 additions & 0 deletions .github/workflows/ci.yml
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@@ -0,0 +1,92 @@
# Copyright 2021 OpenHW Group
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

# Run functional regression checks
name: ci
on: [push, pull_request]

jobs:
install-tools:
name: install-tools
runs-on: ubuntu-latest
env:
NUM_JOBS: 8
steps:
- uses: actions/checkout@v4
with:
submodules: recursive

- name: Verify Verilator installation
run: |
make verilator
- name: Verify GCC installation
run: |
make riscv32-gcc
- name: Verify bender installation
run: |
make bender
- name: Verify Python tools installation
run: |
cd golden-model && source setup-py.sh
# - name: Install
# run: |
# make verilator riscv32-gcc bender; cd golden-model && source setup-py.sh

run-hwpe-tests:
name: run-hwpe-tests
runs-on: ubuntu-latest
env:
Target: verilator
REDMULE_COMPLEX: 0
BENDER: ./bender

needs:
install-tools
steps:
- uses: actions/checkout@v4
with:
submodules: recursive

- name: Install required tools
run: |
make bender
make riscv32-gcc
make verilator
pip3 install numpy
cd golden-model && source setup-py.sh && cd ..
- name: Run Tests
run: |
source scripts/regression-list.sh
run-complex-tests:
name: run-complex-tests
runs-on: ubuntu-latest
env:
Target: verilator
REDMULE_COMPLEX: 1
BENDER: ./bender

needs:
install-tools
steps:
- uses: actions/checkout@v4
with:
submodules: recursive

- name: Install required tools
run: |
make bender
make riscv32-gcc
make verilator
pip3 install numpy
cd golden-model && source setup-py.sh && cd ..
- name: Run Tests
run: |
source scripts/regression-list.sh
File renamed without changes.
8 changes: 4 additions & 4 deletions Bender.lock
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Expand Up @@ -7,8 +7,8 @@ packages:
dependencies:
- common_cells
common_cells:
revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f
version: 1.32.0
revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb
version: 1.37.0
source:
Git: https://github.com/pulp-platform/common_cells.git
dependencies:
Expand Down Expand Up @@ -67,8 +67,8 @@ packages:
dependencies:
- tech_cells_generic
hwpe-stream:
revision: 4c2ef8c33a6e2a8c88127e2153013d4f2dc3f448
version: 1.7.0
revision: 65c99a4a2f37a79acee800ab0151f67dfb1edef1
version: 1.8.0
source:
Git: https://github.com/pulp-platform/hwpe-stream.git
dependencies:
Expand Down
10 changes: 7 additions & 3 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -54,12 +54,16 @@ sources:

- target: any(redmule_test_complex, redmule_test_hwpe)
files:
- tb/tb_dummy_memory.sv
- target/sim/src/tb_dummy_memory.sv

- target: redmule_test_complex
files:
- tb/redmule_complex_tb.sv
- target/sim/src/redmule_complex_tb.sv

- target: redmule_test_hwpe
files:
- tb/redmule_tb.sv
- target/sim/src/redmule_tb.sv

- target: vsim
files:
- target/sim/src/redmule_tb_wrap.sv
150 changes: 74 additions & 76 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -7,30 +7,44 @@
# Top-level Makefile

# Paths to folders
mkfile_path := $(dir $(abspath $(firstword $(MAKEFILE_LIST))))
SW ?= $(mkfile_path)sw
BUILD_DIR ?= $(SW)/build
VSIM_DIR ?= $(mkfile_path)vsim
QUESTA ?= questa-2023.4
BENDER_DIR ?= .
BENDER ?= bender
ISA ?= riscv
ARCH ?= rv
XLEN ?= 32
XTEN ?= imc
RootDir := $(dir $(abspath $(firstword $(MAKEFILE_LIST))))
TargetDir := $(RootDir)target
SimDir := $(TargetDir)/sim
ScriptsDir := $(RootDir)scripts
VerilatorPath := target/sim/verilator
VsimPath := target/sim/vsim
SW ?= $(RootDir)sw
BUILD_DIR ?= $(SW)/build
SIM_DIR ?= $(RootDir)vsim
QUESTA ?= questa-2023.4
BENDER_DIR ?= .
BENDER ?= bender
Gcc ?= $(GccInstallDir)/bin/
ISA ?= riscv
ARCH ?= rv
XLEN ?= 32
XTEN ?= imc_zicsr
PYTHON ?= python3

target ?= verilator
TargetPath := $(SimDir)/$(target)

# Included makefrags
include $(TargetPath)/$(target).mk
include bender_common.mk
include bender_sim.mk
include bender_synth.mk

ifeq ($(REDMULE_COMPLEX),1)
TEST_SRCS := $(SW)/redmule_complex.c
else
TEST_SRCS := $(SW)/redmule.c
endif

compile_script ?= $(mkfile_path)scripts/compile.tcl
compile_script_synth ?= $(mkfile_path)scripts/synth_compile.tcl
compile_flag ?= +acc -permissive -suppress 2583 -suppress 13314
compile_script_synth ?= $(RootDir)scripts/synth_compile.tcl

INI_PATH = $(mkfile_path)modelsim.ini
WORK_PATH = $(VSIM_DIR)/work
INI_PATH = $(RootDir)modelsim.ini
WORK_PATH = $(SIM_DIR)/work

# Useful Parameters
gui ?= 0
Expand All @@ -53,9 +67,9 @@ INC += -I$(SW)/utils
BOOTSCRIPT := $(SW)/kernel/crt0.S
LINKSCRIPT := $(SW)/kernel/link.ld

CC=$(ISA)$(XLEN)-unknown-elf-gcc
CC=$(Gcc)$(ISA)$(XLEN)-unknown-elf-gcc
LD=$(CC)
OBJDUMP=$(ISA)$(XLEN)-unknown-elf-objdump
OBJDUMP=$(Gcc)$(ISA)$(XLEN)-unknown-elf-objdump
CC_OPTS=-march=$(ARCH)$(XLEN)$(XTEN) -mabi=ilp32 -D__$(ISA)__ -O2 -g -Wextra -Wall -Wno-unused-parameter -Wno-unused-variable -Wno-unused-function -Wundef -fdata-sections -ffunction-sections -MMD -MP
LD_OPTS=-march=$(ARCH)$(XLEN)$(XTEN) -mabi=ilp32 -D__$(ISA)__ -MMD -MP -nostartfiles -nostdlib -Wl,--gc-sections

Expand All @@ -64,14 +78,14 @@ CRT=$(BUILD_DIR)/crt0.o
OBJ=$(BUILD_DIR)/verif.o
BIN=$(BUILD_DIR)/verif
DUMP=$(BUILD_DIR)/verif.dump
STIM_INSTR=$(VSIM_DIR)/stim_instr.txt
STIM_DATA=$(VSIM_DIR)/stim_data.txt
STIM_INSTR=$(BUILD_DIR)/stim_instr.txt
STIM_DATA=$(BUILD_DIR)/stim_data.txt

# Build implicit rules
$(STIM_INSTR) $(STIM_DATA): $(BIN)
objcopy --srec-len 1 --output-target=srec $(BIN) $(BIN).s19
scripts/parse_s19.pl $(BIN).s19 > $(BIN).txt
python scripts/s19tomem.py $(BIN).txt $(STIM_INSTR) $(STIM_DATA)
$(PYTHON) scripts/parse_s19.py < $(BIN).s19 > $(BIN).txt
$(PYTHON) scripts/s19tomem.py $(BIN).txt $(STIM_INSTR) $(STIM_DATA)

$(BIN): $(CRT) $(OBJ)
$(LD) $(LD_OPTS) -o $(BIN) $(CRT) $(OBJ) -T$(LINKSCRIPT)
Expand All @@ -90,55 +104,13 @@ SHELL := /bin/bash
# Generate instructions and data stimuli
sw-build: $(STIM_INSTR) $(STIM_DATA) dis

# Run the simulation
run: $(CRT)
ifeq ($(gui), 0)
cd $(VSIM_DIR); \
$(QUESTA) vsim -c $(tb)_opt \
-do "run -a" \
-gSTIM_INSTR=$(STIM_INSTR) \
-gSTIM_DATA=$(STIM_DATA) \
-gPROB_STALL=$(P_STALL)
else
cd $(VSIM_DIR); \
$(QUESTA) vsim $(tb)_opt \
-do "set Testbench $(tb)" \
-do "log -r /*" \
-do "source $(WAVES)" \
-gSTIM_INSTR=$(STIM_INSTR) \
-gSTIM_DATA=$(STIM_DATA) \
-gPROB_STALL=$(P_STALL)
endif

# Download bender
bender:
curl --proto '=https' \
--tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh -s -- 0.24.0

include bender_common.mk
include bender_sim.mk
include bender_synth.mk

WAVES := $(mkfile_path)scripts/wave.tcl

ifeq ($(REDMULE_COMPLEX),1)
tb := redmule_complex_tb
else
tb := redmule_tb
endif

$(VSIM_DIR):
mkdir -p $(VSIM_DIR)

update-ips: $(VSIM_DIR)
$(BENDER) update
$(BENDER) script vsim \
--vlog-arg="$(compile_flag)" \
--vcom-arg="-pedanticerrors" \
$(common_targs) $(common_defs) \
$(sim_targs) \
> ${compile_script}
echo 'vopt $(compile_flag) $(tb) -o $(tb)_opt' >> ${compile_script}
$(SIM_DIR):
mkdir -p $(SIM_DIR)

synth-ips:
$(BENDER) update
Expand All @@ -150,9 +122,6 @@ synth-ips:
sw-clean:
rm -rf $(BUILD_DIR)

hw-clean:
rm -rf $(VSIM_DIR)

dis:
$(OBJDUMP) -d $(BIN) > $(DUMP)

Expand All @@ -168,14 +137,43 @@ golden: golden-clean
golden-clean:
$(MAKE) -C golden-model golden-clean

clean-all: hw-clean sw-clean
rm -rf $(mkfile_path).bender
clean-all: sw-clean
rm -rf $(RootDir).bender
rm -rf $(compile_script)

hw-build: $(VSIM_DIR)
cd $(VSIM_DIR); \
$(QUESTA) vsim -c -do 'quit -code [source $(compile_script)]'

sw-all: sw-clean sw-build

hw-all: hw-clean hw-build
# Install tools
CXX ?= g++
NumCores := $(shell nproc)
NumCoresHalf := $(shell echo "$$(($(NumCores) / 2))")
VendorDir ?= $(RootDir)vendor
InstallDir ?= $(VendorDir)/install
# Verilator
VerilatorVersion ?= v5.028
VerilatorInstallDir := $(InstallDir)/verilator
# GCC
GccInstallDir := $(InstallDir)/riscv
RiscvTarDir := riscv.tar.gz
GccUrl := https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.08.28/riscv32-elf-ubuntu-20.04-gcc-nightly-2024.08.28-nightly.tar.gz

verilator: $(InstallDir)/bin/verilator

$(InstallDir)/bin/verilator:
rm -rf $(VendorDir)/verilator
mkdir -p $(VendorDir) && cd $(VendorDir) && git clone https://github.com/verilator/verilator.git
# Checkout the right version
cd $(VendorDir)/verilator && git reset --hard && git fetch && git checkout $(VerilatorVersion)
# Compile verilator
sudo apt install libfl-dev help2man
mkdir -p $(VerilatorInstallDir) && cd $(VendorDir)/verilator && git clean -xfdf && autoconf && \
./configure --prefix=$(VerilatorInstallDir) CXX=$(CXX) && make -j$(NumCoresHalf) && make install

riscv32-gcc: $(GccInstallDir)

$(GccInstallDir):
rm -rf $(GccInstallDir) $(VendorDir)/$(RiscvTarDir)
mkdir -p $(InstallDir)
cd $(VendorDir) && \
wget $(GccUrl) -O $(RiscvTarDir) && \
tar -xzvf $(RiscvTarDir) -C $(InstallDir) riscv
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