RVAnt 🐜

RVAnt is a minimal implementation of RV32I written in SystemVerilog for individual study purpose.

Table of Contents

• RVAnt 🐜
  • Table of Contents
  • Features
  • Microarchitecture
  • Performance
  • Directory Description
  • Build and Test
  • Documents
  • Contributing

Features

• RV32I[M]_Zicsr_Zifencei
• M-mode only
• 3-stage pipeline
• in-order single issue
• out-of-order execution
• writen in SystemVerilog
• MIT license

Microarchitecture

The microarchitecture of RVAnt:

Performance

Directory Description

Module	Description
rvant	The RVAnt CPU
rvant_axi	The version of the CPU with AXI4-Lite interface
rvant_axi_adapter	Adapter from PicoRV32 Memory Interface to AXI4-Lite
rvant_wb	The version of the CPU with Wishbone Master interface
rvant_pcpi_mul	A PCPI core that implements the MUL[H[SU|U]] instructions
rvant_pcpi_fast_mul	A version of picorv32_pcpi_fast_mul using a single cycle multiplier
rvant_pcpi_div	A PCPI core that implements the DIV[U]/REM[U] instructions

Build and Test

Documents

You can build the documents on your local machine using sphinx,

cd doc
pip3 install -r requirements.txt
make clean
make html

or read the online documents.

Contributing

Check out LowRISC Style Guide. Follow the conventional Commits, it's recommanded to use commitizen with pre-commit enabled.

# install Commitizen and pre-commit
pip3 install -r requirements.txt
pre-commit install
# integrate Commitizen
pre-commit install --hook-type commit-msg