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Avoid using the x86-specific implementations on non-sse2 x86
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Patch from Debian
Fixes briansmith#1999
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jackpot51 committed Oct 18, 2024
1 parent fa98b49 commit fce20f1
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Showing 9 changed files with 55 additions and 40 deletions.
17 changes: 16 additions & 1 deletion build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -427,7 +427,7 @@ fn build_c_code(

generate_prefix_symbols_asm_headers(out_dir, ring_core_prefix).unwrap();

let (asm_srcs, obj_srcs) = if let Some(asm_target) = asm_target {
let (mut asm_srcs, mut obj_srcs) = if let Some(asm_target) = asm_target {
let perlasm_src_dsts = perlasm_src_dsts(asm_dir, asm_target);

if !use_pregenerated {
Expand All @@ -451,6 +451,21 @@ fn build_c_code(
(vec![], vec![])
};

use std::env;

if target.arch == "x86" {
let mut havesse2 = false;
for target_feature in env::var("CARGO_CFG_TARGET_FEATURE").unwrap_or("".to_string()).split(",") {
if target_feature == "sse2" {
havesse2 = true;
}
}
if !havesse2 {
asm_srcs = vec![];
obj_srcs = vec![];
}
}

let core_srcs = sources_for_arch(&target.arch)
.into_iter()
.filter(|p| !is_perlasm(p))
Expand Down
22 changes: 11 additions & 11 deletions src/aead/aes.rs
Original file line number Diff line number Diff line change
Expand Up @@ -149,7 +149,7 @@ impl Key {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
Implementation::HWAES => {
set_encrypt_key!(aes_hw_set_encrypt_key, bytes, key_bits, &mut key)?
Expand All @@ -159,7 +159,7 @@ impl Key {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
Implementation::VPAES_BSAES => {
set_encrypt_key!(vpaes_set_encrypt_key, bytes, key_bits, &mut key)?
Expand All @@ -180,15 +180,15 @@ impl Key {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
Implementation::HWAES => encrypt_block!(aes_hw_encrypt, a, self),

#[cfg(any(
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
Implementation::VPAES_BSAES => encrypt_block!(vpaes_encrypt, a, self),

Expand Down Expand Up @@ -219,7 +219,7 @@ impl Key {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
Implementation::HWAES => {
ctr32_encrypt_blocks!(aes_hw_ctr32_encrypt_blocks, in_out, src, &self.inner, ctr)
Expand Down Expand Up @@ -263,7 +263,7 @@ impl Key {
ctr32_encrypt_blocks!(vpaes_ctr32_encrypt_blocks, in_out, src, &self.inner, ctr)
}

#[cfg(target_arch = "x86")]
#[cfg(all(target_arch = "x86", target_feature = "sse2"))]
Implementation::VPAES_BSAES => {
super::shift::shift_full_blocks(in_out, src, |input| {
self.encrypt_iv_xor_block(ctr.increment(), Block::from(input), cpu_features)
Expand Down Expand Up @@ -365,7 +365,7 @@ pub enum Implementation {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
HWAES = 1,

Expand All @@ -374,7 +374,7 @@ pub enum Implementation {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
VPAES_BSAES = 2,

Expand All @@ -387,7 +387,7 @@ fn detect_implementation(cpu_features: cpu::Features) -> Implementation {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
)))]
let _cpu_features = cpu_features;

Expand All @@ -398,14 +398,14 @@ fn detect_implementation(cpu_features: cpu::Features) -> Implementation {
}
}

#[cfg(any(target_arch = "x86_64", target_arch = "x86"))]
#[cfg(any(target_arch = "x86_64", all(target_arch = "x86", target_feature = "sse2")))]
{
if cpu::intel::AES.available(cpu_features) {
return Implementation::HWAES;
}
}

#[cfg(any(target_arch = "x86_64", target_arch = "x86"))]
#[cfg(any(target_arch = "x86_64", all(target_arch = "x86", target_feature = "sse2")))]
{
if cpu::intel::SSSE3.available(cpu_features) {
return Implementation::VPAES_BSAES;
Expand Down
12 changes: 6 additions & 6 deletions src/aead/chacha.rs
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ use super::{quic::Sample, Nonce};
not(any(
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86",
all(target_arch = "x86", target_feature = "sse2"),
target_arch = "x86_64"
))
))]
Expand Down Expand Up @@ -75,7 +75,7 @@ impl Key {
// has this limitation and come up with a better solution.
//
// https://rt.openssl.org/Ticket/Display.html?id=4362
if cfg!(any(target_arch = "arm", target_arch = "x86")) && src.start != 0 {
if cfg!(any(target_arch = "arm", all(target_arch = "x86", target_feature = "sse2"))) && src.start != 0 {
let len = in_out.len() - src.start;
in_out.copy_within(src, 0);
self.encrypt_in_place(counter, &mut in_out[..len]);
Expand All @@ -91,7 +91,7 @@ impl Key {
#[cfg(any(
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86",
all(target_arch = "x86", target_feature = "sse2"),
target_arch = "x86_64"
))]
#[inline(always)]
Expand Down Expand Up @@ -128,7 +128,7 @@ impl Key {
#[cfg(not(any(
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86",
all(target_arch = "x86", target_feature = "sse2"),
target_arch = "x86_64"
)))]
use fallback::ChaCha20_ctr32;
Expand Down Expand Up @@ -169,7 +169,7 @@ impl Counter {
not(any(
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86",
all(target_arch = "x86", target_feature = "sse2"),
target_arch = "x86_64"
))
))]
Expand Down Expand Up @@ -219,7 +219,7 @@ mod tests {
let max_offset = if cfg!(any(
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86",
all(target_arch = "x86", target_feature = "sse2"),
target_arch = "x86_64"
)) {
MAX_ALIGNMENT_AND_OFFSET
Expand Down
12 changes: 6 additions & 6 deletions src/aead/gcm.rs
Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,7 @@ impl Key {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
Implementation::CLMUL => {
prefixed_extern! {
Expand Down Expand Up @@ -185,7 +185,7 @@ impl Context {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
Implementation::CLMUL => {
prefixed_extern! {
Expand Down Expand Up @@ -236,7 +236,7 @@ impl Context {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
Implementation::CLMUL => {
prefixed_extern! {
Expand Down Expand Up @@ -339,7 +339,7 @@ enum Implementation {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
CLMUL,

Expand All @@ -356,7 +356,7 @@ fn detect_implementation(cpu_features: cpu::Features) -> Implementation {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
)))]
let _cpu_features = cpu_features;

Expand All @@ -367,7 +367,7 @@ fn detect_implementation(cpu_features: cpu::Features) -> Implementation {
}
}

#[cfg(any(target_arch = "x86_64", target_arch = "x86"))]
#[cfg(any(target_arch = "x86_64", all(target_arch = "x86", target_feature = "sse2")))]
{
if cpu::intel::FXSR.available(cpu_features) && cpu::intel::PCLMULQDQ.available(cpu_features)
{
Expand Down
2 changes: 1 addition & 1 deletion src/aead/shift.rs
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@

use super::block::{Block, BLOCK_LEN};

#[cfg(target_arch = "x86")]
#[cfg(all(target_arch = "x86", target_feature = "sse2"))]
pub fn shift_full_blocks<F>(in_out: &mut [u8], src: core::ops::RangeFrom<usize>, mut transform: F)
where
F: FnMut(&[u8; BLOCK_LEN]) -> Block,
Expand Down
10 changes: 5 additions & 5 deletions src/arithmetic/montgomery.rs
Original file line number Diff line number Diff line change
Expand Up @@ -128,7 +128,7 @@ unsafe fn mul_mont(
#[cfg(not(any(
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86",
all(target_arch = "x86", target_feature = "sse2"),
target_arch = "x86_64"
)))]
// TODO: Stop calling this from C and un-export it.
Expand Down Expand Up @@ -168,7 +168,7 @@ prefixed_export! {
not(any(
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86",
all(target_arch = "x86", target_feature = "sse2"),
target_arch = "x86_64"
))
))]
Expand Down Expand Up @@ -201,7 +201,7 @@ pub(super) fn limbs_from_mont_in_place(r: &mut [Limb], tmp: &mut [Limb], m: &[Li
#[cfg(not(any(
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86",
all(target_arch = "x86", target_feature = "sse2"),
target_arch = "x86_64"
)))]
fn limbs_mul(r: &mut [Limb], a: &[Limb], b: &[Limb]) {
Expand All @@ -223,7 +223,7 @@ fn limbs_mul(r: &mut [Limb], a: &[Limb], b: &[Limb]) {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))
))]
prefixed_extern! {
Expand All @@ -236,7 +236,7 @@ prefixed_extern! {
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86_64",
target_arch = "x86"
all(target_arch = "x86", target_feature = "sse2")
))]
prefixed_extern! {
// `r` and/or 'a' and/or 'b' may alias.
Expand Down
6 changes: 3 additions & 3 deletions src/cpu.rs
Original file line number Diff line number Diff line change
Expand Up @@ -27,13 +27,13 @@ pub(crate) fn features() -> Features {
#[cfg(any(target_arch = "aarch64", target_arch = "arm"))]
use arm::init_global_shared_with_assembly;

#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
#[cfg(any(all(target_arch = "x86", target_feature = "sse2"), target_arch = "x86_64"))]
use intel::init_global_shared_with_assembly;

#[cfg(any(
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86",
all(target_arch = "x86", target_feature = "sse2"),
target_arch = "x86_64",
))]
{
Expand All @@ -47,5 +47,5 @@ pub(crate) fn features() -> Features {
#[cfg(any(target_arch = "aarch64", target_arch = "arm"))]
pub mod arm;

#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
#[cfg(any(all(target_arch = "x86", target_feature = "sse2"), target_arch = "x86_64"))]
pub mod intel;
12 changes: 6 additions & 6 deletions src/cpu/intel.rs
Original file line number Diff line number Diff line change
Expand Up @@ -13,11 +13,11 @@
// CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

#![cfg_attr(
not(any(target_arch = "x86", target_arch = "x86_64")),
not(any(all(target_arch = "x86", target_feature = "sse2"), target_arch = "x86_64")),
allow(dead_code)
)]

#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
#[cfg(any(all(target_arch = "x86", target_feature = "sse2"), target_arch = "x86_64"))]
mod abi_assumptions {
// TOOD: Support targets that do not have SSE and SSE2 enabled, such as
// x86_64-unknown-linux-none. See
Expand All @@ -29,7 +29,7 @@ mod abi_assumptions {

#[cfg(target_arch = "x86_64")]
const _ASSUMED_POINTER_SIZE: usize = 8;
#[cfg(target_arch = "x86")]
#[cfg(all(target_arch = "x86", target_feature = "sse2"))]
const _ASSUMED_POINTER_SIZE: usize = 4;
const _ASSUMED_USIZE_SIZE: () = assert!(core::mem::size_of::<usize>() == _ASSUMED_POINTER_SIZE);
const _ASSUMED_REF_SIZE: () =
Expand All @@ -43,7 +43,7 @@ pub(crate) struct Feature {
mask: u32,
}

#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
#[cfg(any(all(target_arch = "x86", target_feature = "sse2"), target_arch = "x86_64"))]
pub(super) unsafe fn init_global_shared_with_assembly() {
prefixed_extern! {
fn OPENSSL_cpuid_setup();
Expand All @@ -57,15 +57,15 @@ impl Feature {
#[allow(clippy::needless_return)]
#[inline(always)]
pub fn available(&self, _: super::Features) -> bool {
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
#[cfg(any(all(target_arch = "x86", target_feature = "sse2"), target_arch = "x86_64"))]
{
prefixed_extern! {
static mut OPENSSL_ia32cap_P: [u32; 4];
}
return self.mask == self.mask & unsafe { OPENSSL_ia32cap_P[self.word] };
}

#[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
#[cfg(not(any(all(target_arch = "x86", target_feature = "sse2"), target_arch = "x86_64")))]
{
return false;
}
Expand Down
2 changes: 1 addition & 1 deletion src/prefixed.rs
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ macro_rules! prefixed_extern {
#[cfg(not(any(
target_arch = "aarch64",
target_arch = "arm",
target_arch = "x86",
all(target_arch = "x86", target_feature = "sse2"),
target_arch = "x86_64"
)))]
macro_rules! prefixed_export {
Expand Down

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