COMPUTE_SLICES global parameter as simple define

rejunity · Mar 19, 2024 · 57fb840 · 57fb840
1 parent cd2ba62
commit 57fb840
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Showing 3 changed files with 6 additions and 10 deletions.
diff --git a/src/1_58bit_mul.v b/src/1_58bit_mul.v
@@ -22,9 +22,9 @@
 
 `define default_netname none
 
-module tt_um_rejunity_1_58bit #(
-    parameter integer COMPUTE_SLICES = `COMPUTE_SLICES
-) (
+`define COMPUTE_SLICES 1
+
+module tt_um_rejunity_1_58bit (
     input  wire [7:0] ui_in,    // Dedicated inputs
     output wire [7:0] uo_out,   // Dedicated outputs
     input  wire [7:0] uio_in,   // IOs: Input path
@@ -58,7 +58,7 @@ module tt_um_rejunity_1_58bit #(
     // @TODO: special weight to initiate readout
     wire       initiate_read_out = !ena;
 
-    systolic_array #(.SLICES(COMPUTE_SLICES)) systolic_array (
+    systolic_array systolic_array (
         .clk(clk),
         .reset(reset),
 
@@ -77,7 +77,7 @@ module tt_um_rejunity_1_58bit #(
 endmodule
 
 module systolic_array #(
-    parameter integer SLICES = 1
+    parameter integer SLICES = `COMPUTE_SLICES
 ) (
     input  wire       clk,
     input  wire       reset,

diff --git a/test/Makefile b/test/Makefile
@@ -1,10 +1,6 @@
 # Makefile
 # See https://docs.cocotb.org/en/stable/quickstart.html for more info
 
-# global parameters
-COMPUTE_SLICES ?= 2
-COMPILE_ARGS += -DCOMPUTE_SLICES=$(COMPUTE_SLICES)
-
 # defaults
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog

diff --git a/test/tb.v b/test/tb.v
@@ -26,7 +26,7 @@ module tb ();
     parameter integer COMPUTE_SLICES = `COMPUTE_SLICES;
 
     // Replace tt_um_example with your module name:
-    tt_um_rejunity_1_58bit #(.COMPUTE_SLICES(COMPUTE_SLICES)) user_project (
+    tt_um_rejunity_1_58bit user_project (
         // Include power ports for the Gate Level test:
         `ifdef GL_TEST
             .VPWR(1'b1),