Increased output queue to 16 for 2 slice systolic array.

rejunity · Mar 10, 2024 · b8d46be · b8d46be
1 parent b5b3d20
commit b8d46be
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/src/1_58bit_mul.v b/src/1_58bit_mul.v
@@ -89,7 +89,8 @@ module systolic_array (
     reg  signed [16:0] accumulators      [W*H-1:0];
     wire signed [16:0] accumulators_next [W*H-1:0];
     reg  signed [16:0] out_queue         [W*H-1:0];
-    reg          [1:0] out_queue_index;
+    // reg          [1:0] out_queue_index;
+    reg          [3:0] out_queue_index;
 
     integer n;
     always @(posedge clk) begin