add support for mcountinhibit CSR

We hardwired mcountinihibit to 0 previously. Now, we implemented it. Signed-off-by: Yangyu Chen <[email protected]>
riscv-software-src · Sep 1, 2024 · 51ffe73 · 51ffe73
1 parent 3c5b1bb
commit 51ffe73
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Showing 4 changed files with 14 additions and 3 deletions.
diff --git a/riscv/csr_init.cc b/riscv/csr_init.cc
@@ -86,7 +86,6 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa)
       add_csr(which_mevent, mevent[i]);
     }
   }
-  add_csr(CSR_MCOUNTINHIBIT, std::make_shared<const_csr_t>(proc, CSR_MCOUNTINHIBIT, 0));
   add_const_ext_csr(EXT_SSCOFPMF, CSR_SCOUNTOVF, std::make_shared<scountovf_csr_t>(proc, CSR_SCOUNTOVF));
   add_csr(CSR_MIE, mie = std::make_shared<mie_csr_t>(proc, CSR_MIE));
   add_csr(CSR_MIP, mip = std::make_shared<mip_csr_t>(proc, CSR_MIP));
@@ -134,6 +133,7 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa)
   add_supervisor_csr(CSR_MIDELEG, mideleg = std::make_shared<mideleg_csr_t>(proc, CSR_MIDELEG));
   const reg_t counteren_mask = (proc->extension_enabled_const(EXT_ZICNTR) ? 0x7UL : 0x0) | (proc->extension_enabled_const(EXT_ZIHPM) ? 0xfffffff8ULL : 0x0);
   add_user_csr(CSR_MCOUNTEREN, mcounteren = std::make_shared<masked_csr_t>(proc, CSR_MCOUNTEREN, counteren_mask, 0));
+  add_csr(CSR_MCOUNTINHIBIT, mcountinhibit = std::make_shared<masked_csr_t>(proc, CSR_MCOUNTINHIBIT, counteren_mask & (~HPM_TIME), 0));
   add_supervisor_csr(CSR_SCOUNTEREN, scounteren = std::make_shared<masked_csr_t>(proc, CSR_SCOUNTEREN, counteren_mask, 0));
   nonvirtual_sepc = std::make_shared<epc_csr_t>(proc, CSR_SEPC);
   add_hypervisor_csr(CSR_VSEPC, vsepc = std::make_shared<epc_csr_t>(proc, CSR_VSEPC));

diff --git a/riscv/encoding.h b/riscv/encoding.h
@@ -173,6 +173,14 @@
 #define SIP_SSIP MIP_SSIP
 #define SIP_STIP MIP_STIP
 
+#define HPM_CY_SHIFT    0
+#define HPM_TIME_SHIFT  1
+#define HPM_IR_SHIFT    2
+
+#define HPM_CY      (1ULL << HPM_CY_SHIFT)
+#define HPM_TIME    (1ULL << HPM_TIME_SHIFT)
+#define HPM_IR      (1ULL << HPM_IR_SHIFT)
+
 #define MENVCFG_FIOM  0x00000001
 #define MENVCFG_LPE   0x00000004
 #define MENVCFG_SSE   0x00000008

diff --git a/riscv/execute.cc b/riscv/execute.cc
@@ -364,10 +364,12 @@ void processor_t::step(size_t n)
       in_wfi = true;
     }
 
-    state.minstret->bump(instret);
+    if (!(state.mcountinhibit->read() & HPM_IR))
+      state.minstret->bump(instret);
 
     // Model a hart whose CPI is 1.
-    state.mcycle->bump(instret);
+    if (!(state.mcountinhibit->read() & HPM_CY))
+      state.mcycle->bump(instret);
 
     n -= instret;
   }

diff --git a/riscv/processor.h b/riscv/processor.h
@@ -99,6 +99,7 @@ struct state_t
   csr_t_p medeleg;
   csr_t_p mideleg;
   csr_t_p mcounteren;
+  csr_t_p mcountinhibit;
   csr_t_p mevent[N_HPMCOUNTERS];
   csr_t_p mnstatus;
   csr_t_p mnepc;