Fix non-standard interrupt start position

Signed-off-by: demin.han <[email protected]>
riscv-software-src · Oct 8, 2024 · d32c5d5 · d32c5d5
1 parent 824ecdf
commit d32c5d5
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/riscv/processor.cc b/riscv/processor.cc
@@ -304,8 +304,8 @@ void processor_t::take_interrupt(reg_t pending_interrupts)
   const bool nmie = !(state.mnstatus && !get_field(state.mnstatus->read(), MNSTATUS_NMIE));
   if (!state.debug_mode && nmie && enabled_interrupts) {
     // nonstandard interrupts have highest priority
-    if (enabled_interrupts >> (IRQ_M_EXT + 1))
-      enabled_interrupts = enabled_interrupts >> (IRQ_M_EXT + 1) << (IRQ_M_EXT + 1);
+    if (enabled_interrupts >> 16)
+      enabled_interrupts = enabled_interrupts >> 16 << 16;
     // standard interrupt priority is MEI, MSI, MTI, SEI, SSI, STI
     else if (enabled_interrupts & MIP_MEIP)
       enabled_interrupts = MIP_MEIP;