ADD: a basic BTM N-trace spec compliant trace encoder model

riscv/execute.cc

@@ -2,9 +2,12 @@
 
 #include "config.h"
 #include "processor.h"
+#include "trace_ingress.h"
+#include "trace_encoder_n.h"
 #include "mmu.h"
 #include "disasm.h"
 #include "decode_macros.h"
+#include "trace_ingress.h"
 #include <cassert>
 
 static void commit_log_reset(processor_t* p)
@@ -162,6 +165,7 @@ inline void processor_t::update_histogram(reg_t pc)
 static inline reg_t execute_insn_fast(processor_t* p, reg_t pc, insn_fetch_t fetch) {
   return fetch.func(p, fetch.insn, pc);
 }
+
 static inline reg_t execute_insn_logged(processor_t* p, reg_t pc, insn_fetch_t fetch)
 {
   if (p->get_log_commits_enabled()) {
@@ -173,6 +177,21 @@ static inline reg_t execute_insn_logged(processor_t* p, reg_t pc, insn_fetch_t f
 
   try {
     npc = fetch.func(p, fetch.insn, pc);
+
+    if (p->get_trace_enabled()) {
+      hart_to_encoder_ingress_t packet {
+        .i_type = _get_insn_type(&fetch.insn, npc != p->get_state()->pc + insn_length(fetch.insn.bits())),
+        .exc_cause = 0,
+        .tval = 0,
+        .priv = P_M, // TODO: check for processor privilege level
+        .i_addr = pc,
+        .iretire = 1,
+        .ilastsize = insn_length(fetch.insn.bits())/2,
+        .i_timestamp = p->get_state()->mcycle->read(),
+      };
+      p->trace_encoder.push_commit(packet);
+    }
+
     if (npc != PC_SERIALIZE_BEFORE) {
       if (p->get_log_commits_enabled()) {
         commit_log_print_insn(p, pc, fetch.insn);
@@ -205,7 +224,7 @@ static inline reg_t execute_insn_logged(processor_t* p, reg_t pc, insn_fetch_t f
 bool processor_t::slow_path()
 {
   return debug || state.single_step != state.STEP_NONE || state.debug_mode ||
-         log_commits_enabled || histogram_enabled || in_wfi || check_triggers_icount;
+         log_commits_enabled || histogram_enabled || in_wfi || check_triggers_icount || trace_enabled;
 }
 
 // fetch/decode/execute loop

riscv/processor.cc

@@ -12,6 +12,7 @@
 #include "platform.h"
 #include "vector_unit.h"
 #include "debug_defines.h"
+#include "trace_encoder_n.h"
 #include <cinttypes>
 #include <cmath>
 #include <cstdlib>
@@ -182,6 +183,11 @@ void processor_t::enable_log_commits()
   log_commits_enabled = true;
 }
 
+void processor_t::enable_trace()
+{
+  trace_enabled = true;
+}
+
 void processor_t::reset()
 {
   xlen = isa.get_max_xlen();
@@ -204,6 +210,8 @@ void processor_t::reset()
 
   if (sim)
     sim->proc_reset(id);
+
+  trace_encoder.reset();
 }
 
 extension_t* processor_t::get_extension()

riscv/processor.h

@@ -17,6 +17,7 @@
 #include "triggers.h"
 #include "../fesvr/memif.h"
 #include "vector_unit.h"
+#include "trace_encoder_n.h"
 
 #define FIRST_HPMCOUNTER 3
 #define N_HPMCOUNTERS 29
@@ -253,7 +254,9 @@ class processor_t : public abstract_device_t
   void set_debug(bool value);
   void set_histogram(bool value);
   void enable_log_commits();
+  void enable_trace();
   bool get_log_commits_enabled() const { return log_commits_enabled; }
+  bool get_trace_enabled() const { return trace_enabled; }
   void reset();
   void step(size_t n); // run for n cycles
   void put_csr(int which, reg_t val);
@@ -367,6 +370,8 @@ class processor_t : public abstract_device_t
 
   void check_if_lpad_required();
 
+  trace_encoder_n* get_trace_encoder() { return &trace_encoder; }
+
 private:
   const isa_parser_t isa;
   const cfg_t * const cfg;
@@ -380,6 +385,7 @@ class processor_t : public abstract_device_t
   unsigned xlen;
   bool histogram_enabled;
   bool log_commits_enabled;
+  bool trace_enabled; // whether core needs to trace instructions - does not mean the encoder itself is enabled!
   FILE *log_file;
   std::ostream sout_; // needed for socket command interface -s, also used for -d and -l, but not for --log
   bool halt_on_reset;
@@ -432,6 +438,7 @@ class processor_t : public abstract_device_t
 
   vectorUnit_t VU;
   triggers::module_t TM;
+  trace_encoder_n trace_encoder;
 };
 
 #endif

riscv/riscv.mk.in

@@ -44,6 +44,8 @@ riscv_install_hdrs = \
 	trap.h \
 	triggers.h \
 	vector_unit.h \
+	trace_ingress.h \
+	trace_encoder_n.h \
 
 riscv_precompiled_hdrs = \
 	insn_template.h \
@@ -73,6 +75,7 @@ riscv_srcs = \
 	vector_unit.cc \
 	socketif.cc \
 	cfg.cc \
+	trace_encoder_n.cc \
 	$(riscv_gen_srcs) \
 
 riscv_test_srcs = \

riscv/sim.cc

@@ -316,15 +316,20 @@ void sim_t::set_histogram(bool value)
   }
 }
 
-void sim_t::configure_log(bool enable_log, bool enable_commitlog)
+void sim_t::configure_log(bool enable_log, bool enable_commitlog, bool trace)
 {
   log = enable_log;
 
-  if (!enable_commitlog)
-    return;
+  if (enable_commitlog) {
+    for (processor_t *proc : procs) {
+      proc->enable_log_commits();
+    }
+  }
 
-  for (processor_t *proc : procs) {
-    proc->enable_log_commits();
+  if (trace) {
+    for (processor_t *proc : procs) {
+      proc->enable_trace();
+    }
   }
 }
 

riscv/sim.h

@@ -48,7 +48,7 @@ class sim_t : public htif_t, public simif_t
   //
   // If enable_log is true, an instruction trace will be generated. If
   // enable_commitlog is true, so will the commit results
-  void configure_log(bool enable_log, bool enable_commitlog);
+  void configure_log(bool enable_log, bool enable_commitlog, bool trace);
 
   void set_procs_debug(bool value);
   void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {