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Address github comments
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Signed-off-by: Dmitriy Ryabtsev <[email protected]>
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Dmitriy Ryabtsev committed Sep 26, 2024
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8 changes: 5 additions & 3 deletions adoc_event_tables/cache_retired.adoc
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|CACHE.L2.LOAD.ACCESS.RET |Retired load instruction which got data from L2 or from some next level in memory hierarchy - L3 cache, local mmemory, remote cache, remote memory, etc.
|CACHE.L2.LOAD.MISS.RET |Retired load instruction which got data from some next level (relative to L2) in memory hierarchy - L3 cache, local mmemory, remote cache, remote memory, etc.
|CACHE.L2.LOAD.HIT.RET |Retired load instruction which got data from L2 cache
|CACHE.L2.LOAD.MERGE.RET |Retired load instruction which hit L2 cache with data not yet in cache but was already requested by preceding miss
|CACHE.L3.LOAD.ACCESS.RET |Retired load instruction which got data from L3 cache or from some next level in memory hierarchy - local mmemory, remote cache, remote memory, etc.
|CACHE.L3.LOAD.MISS.RET |Retired load instruction which got data from some next level (relative to L3) in memory hierarchy - local mmemory, remote cache, remote memory, etc.
|CACHE.L3.LOAD.HIT.RET |Retired load instruction which got data from L3 cache
|CACHE.L3.LOAD.MISS.LOCAL_MEMORY.RET |Retired load instruction which got data from local memory.
|CACHE.L3.LOAD.MISS.REMOTE_MEMORY.RET |Retired load instruction which got data from remote memory (memory attached to remote socket).
|CACHE.L3.LOAD.MISS.REMOTE_CACHE.RET |Retired load instruction which got data from remote cache (cache on remote socket).
|CACHE.L3.LOAD.MERGE.RET |Retired load instruction which hit L3 cache with data not yet in cache but was already requested by preceding miss
|CACHE.LOAD.LOCAL_MEMORY.RET |Retired load instruction which got data from local memory.
|CACHE.LOAD.REMOTE_MEMORY.RET |Retired load instruction which got data from remote memory (memory attached to remote socket).
|CACHE.LOAD.REMOTE_CACHE.RET |Retired load instruction which got data from remote cache (cache on remote socket).
|===

20 changes: 10 additions & 10 deletions adoc_event_tables/cache_retired_metrics.adoc
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[width="100%",cols="25%,40%,35%",options="header",]
|===
|Name |Description |Formula
|CACHE.L1D.LOAD.MPKI.RET |The rate of retired L1 data load cache misses per kilo instructions retired |CACHE.L1D.LOAD.MISS.RET / RETIRED.INST * 1000
|CACHE.L1D.LOAD.MISS.RATE.RET |The ratio of retired L1D cache load misses to the total number of retired L1D load accesses |CACHE.L1D.LOAD.MISS.RET / CACHE.L1D.LOAD.ACCESS.RET
|CACHE.L1D.LOAD.MERGE.PKI.RET |The rate of retired L1 data load cache misses which merged with previous cache miss per kilo instructions retired |CACHE.L1D.LOAD.MERGE.RET / RETIRED.INST * 1000
|CACHE.L1I.MPKI.RET |The rate of retired instructions with L1 instruction cache misses per kilo instructions retired |CACHE.L1I.MISS.RET / RETIRED.INST * 1000
|CACHE.L1D.STORE.MPKI.RET |The rate of retired L1 data store cache misses per kilo instructions retired |CACHE.L1D.STORE.MISS.RET / RETIRED.INST * 1000
|CACHE.L1D.STORE.MISS.RATE.RET |The ratio of retired L1D cache store misses to the total number of retired L1D store accesses |CACHE.L1D.STORE.MISS.RET / CACHE.L1D.STORE.ACCESS.RET
|CACHE.L2.LOAD.MPKI.RET |The rate of retired L2 data load cache misses per kilo instructions retired |CACHE.L2.LOAD.MISS.RET / RETIRED.INST * 1000
|CACHE.L2.LOAD.MISS.RATE.RET |The ratio of retired L2 cache load misses to the total number of retired L2 load accesses |CACHE.L2.LOAD.MISS.RET / CACHE.L2.LOAD.ACCESS.RET
|CACHE.L3.LOAD.MPKI.RET |The rate of retired L3 data load cache misses per kilo instructions retired |CACHE.L3.LOAD.MISS.RET / RETIRED.INST * 1000
|CACHE.L3.LOAD.MISS.RATE.RET |The ratio of retired L3 cache load misses to the total number of retired L3 load accesses |CACHE.L3.LOAD.MISS.RET / CACHE.L3.LOAD.ACCESS.RET
|CACHE.L1D.LOAD.RET.MPKI |The rate of retired L1 data load cache misses per kilo instructions retired |CACHE.L1D.LOAD.MISS.RET / INST.RET * 1000
|CACHE.L1D.LOAD.MISS.RET.RATE |The ratio of retired L1D cache load misses to the total number of retired L1D load accesses |CACHE.L1D.LOAD.MISS.RET / CACHE.L1D.LOAD.ACCESS.RET
|CACHE.L1D.LOAD.MERGE.RET.PKI |The rate of retired L1 data load cache misses which merged with previous cache miss per kilo instructions retired |CACHE.L1D.LOAD.MERGE.RET / INST.RET * 1000
|CACHE.L1I.RET.MPKI |The rate of retired instructions with L1 instruction cache misses per kilo instructions retired |CACHE.L1I.MISS.RET / INST.RET * 1000
|CACHE.L1D.STORE.RET.MPKI |The rate of retired L1 data store cache misses per kilo instructions retired |CACHE.L1D.STORE.MISS.RET / INST.RET * 1000
|CACHE.L1D.STORE.MISS.RET.RATE |The ratio of retired L1D cache store misses to the total number of retired L1D store accesses |CACHE.L1D.STORE.MISS.RET / CACHE.L1D.STORE.ACCESS.RET
|CACHE.L2.LOAD.RET.MPKI |The rate of retired L2 data load cache misses per kilo instructions retired |CACHE.L2.LOAD.MISS.RET / INST.RET * 1000
|CACHE.L2.LOAD.MISS.RET.RATE |The ratio of retired L2 cache load misses to the total number of retired L2 load accesses |CACHE.L2.LOAD.MISS.RET / CACHE.L2.LOAD.ACCESS.RET
|CACHE.L3.LOAD.RET.MPKI |The rate of retired L3 data load cache misses per kilo instructions retired |CACHE.L3.LOAD.MISS.RET / INST.RET * 1000
|CACHE.L3.LOAD.MISS.RET.RATE |The ratio of retired L3 cache load misses to the total number of retired L3 load accesses |CACHE.L3.LOAD.MISS.RET / CACHE.L3.LOAD.ACCESS.RET
|===

44 changes: 22 additions & 22 deletions adoc_event_tables/cache_spec_metrics.adoc
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[width="100%",cols="25%,40%,35%",options="header",]
|===
|Name |Description |Formula
|CACHE.L1D.LOAD.MPKI.SPEC |The rate of speculative L1 data cache misses caused by data loads per kilo instructions retired |CACHE.L1D.LOAD.MISS.SPEC / RETIRED.INST * 1000
|CACHE.L1D.LOAD.MISS.RATE.SPEC |The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data loads |CACHE.L1D.LOAD.MISS.SPEC / CACHE.L1D.LOAD.ACCESS.SPEC
|CACHE.L1D.LOAD.MERGE.PKI.SPEC |The rate of speculative L1 data cache accesses which merged with previous cache miss per kilo instructions retired |CACHE.L1D.LOAD.MERGE.SPEC / RETIRED.INST * 1000
|CACHE.L1D.STORE.MPKI.SPEC |The rate of speculative L1 data cache misses caused by data stores per kilo instructions retired |CACHE.L1D.STORE.MISS.SPEC / RETIRED.INST * 1000
|CACHE.L1D.STORE.MISS.RATE.SPEC |The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data stores |CACHE.L1D.STORE.MISS.SPEC / CACHE.L1D.STORE.ACCESS.SPEC
|CACHE.L1D.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L1D to next level cache per kilo instructions retired |CACHE.L1D.PREF.ISSUED / RETIRED.INST * 1000
|CACHE.L1D.LOAD.SPEC.MPKI |The rate of speculative L1 data cache misses caused by data loads per kilo instructions retired |CACHE.L1D.LOAD.MISS.SPEC / INST.RET * 1000
|CACHE.L1D.LOAD.MISS.SPEC.RATE |The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data loads |CACHE.L1D.LOAD.MISS.SPEC / CACHE.L1D.LOAD.ACCESS.SPEC
|CACHE.L1D.LOAD.MERGE.SPEC.PKI |The rate of speculative L1 data cache accesses which merged with previous cache miss per kilo instructions retired |CACHE.L1D.LOAD.MERGE.SPEC / INST.RET * 1000
|CACHE.L1D.STORE.SPEC.MPKI |The rate of speculative L1 data cache misses caused by data stores per kilo instructions retired |CACHE.L1D.STORE.MISS.SPEC / INST.RET * 1000
|CACHE.L1D.STORE.MISS.SPEC.RATE |The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data stores |CACHE.L1D.STORE.MISS.SPEC / CACHE.L1D.STORE.ACCESS.SPEC
|CACHE.L1D.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L1D to next level cache per kilo instructions retired |CACHE.L1D.PREF.ISSUED / INST.RET * 1000
|CACHE.L1D.PREF.UNUSED.RATE |The ratio of unused cachelines brought into L1D by prefetcher to the total number of prefetcher requests issued by L1D |CACHE.L1D.PREF.UNUSED / CACHE.L1D.PREF.ISSUED
|CACHE.L1I.MPKI.SPEC |The rate of L1 instruction cache misses per kilo instructions retired |CACHE.L1I.MISS.SPEC / RETIRED.INST * 1000
|CACHE.L1I.MISS.RATE.SPEC |The ratio of L1 instruction cache misses to the total number of L1I accesses |CACHE.L1I.MISS.SPEC / CACHE.L1I.ACCESS.SPEC
|CACHE.L1I.MERGE.PKI.SPEC |The rate of L1 instruction cache accesses which merged with previous cache miss per kilo instructions retired |CACHE.L1I.MERGE.SPEC / RETIRED.INST * 1000
|CACHE.L1I.SPEC.MPKI |The rate of L1 instruction cache misses per kilo instructions retired |CACHE.L1I.MISS.SPEC / INST.RET * 1000
|CACHE.L1I.MISS.SPEC.RATE |The ratio of L1 instruction cache misses to the total number of L1I accesses |CACHE.L1I.MISS.SPEC / CACHE.L1I.ACCESS.SPEC
|CACHE.L1I.MERGE.SPEC.PKI |The rate of L1 instruction cache accesses which merged with previous cache miss per kilo instructions retired |CACHE.L1I.MERGE.SPEC / INST.RET * 1000
|CACHE.L1I.MISS.IMPACT |The approximate ratio of cycles lost due to L1I misses |CACHE.L1I.MISS_OUTSTANDING.CYCLES / CYCLES.HART
|CACHE.L2.LOAD.MPKI.SPEC |The rate of speculative L2 cache misses caused by data loads per kilo instructions retired |CACHE.L2.LOAD.MISS.SPEC / RETIRED.INST * 1000
|CACHE.L2.LOAD.MISS.RATE.SPEC |The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data loads |CACHE.L2.LOAD.MISS.SPEC / CACHE.L2.LOAD.ACCESS.SPEC
|CACHE.L2.STORE.MPKI.SPEC |The rate of speculative L2 cache misses caused by data stores per kilo instructions retired |CACHE.L2.STORE.MISS.SPEC / RETIRED.INST * 1000
|CACHE.L2.STORE.MISS.RATE.SPEC |The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data stores |CACHE.L2.STORE.MISS.SPEC / CACHE.L2.STORE.ACCESS.SPEC
|CACHE.L2.STORE.HIT.RFO.PKI.SPEC |The rate of L2 cache hits for store instructions with the purpose to get exclusive ownership per kilo instructions retired |CACHE.L2.STORE.HIT.RFO.SPEC / RETIRED.INST * 1000
|CACHE.L2.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L2 to next level cache per kilo instructions retired |CACHE.L2.PREF.ISSUED / RETIRED.INST * 1000
|CACHE.L2.PREF.MPKI |The rate of L2 cache misses caused by prefetcher per kilo instructions retired |CACHE.L2.PREF.MISS / RETIRED.INST * 1000
|CACHE.L2.LOAD.SPEC.MPKI |The rate of speculative L2 cache misses caused by data loads per kilo instructions retired |CACHE.L2.LOAD.MISS.SPEC / INST.RET * 1000
|CACHE.L2.LOAD.MISS.SPEC.RATE |The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data loads |CACHE.L2.LOAD.MISS.SPEC / CACHE.L2.LOAD.ACCESS.SPEC
|CACHE.L2.STORE.SPEC.MPKI |The rate of speculative L2 cache misses caused by data stores per kilo instructions retired |CACHE.L2.STORE.MISS.SPEC / INST.RET * 1000
|CACHE.L2.STORE.MISS.SPEC.RATE |The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data stores |CACHE.L2.STORE.MISS.SPEC / CACHE.L2.STORE.ACCESS.SPEC
|CACHE.L2.STORE.HIT.RFO.SPEC.PKI |The rate of L2 cache hits for store instructions with the purpose to get exclusive ownership per kilo instructions retired |CACHE.L2.STORE.HIT.RFO.SPEC / INST.RET * 1000
|CACHE.L2.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L2 to next level cache per kilo instructions retired |CACHE.L2.PREF.ISSUED / INST.RET * 1000
|CACHE.L2.PREF.MPKI |The rate of L2 cache misses caused by prefetcher per kilo instructions retired |CACHE.L2.PREF.MISS / INST.RET * 1000
|CACHE.L2.PREF.UNUSED.RATE |The ratio of unused cachelines brought into L2 by prefetcher to the total number of prefetcher requests issued by L2 |CACHE.L2.PREF.UNUSED / CACHE.L2.PF.ISSUED
|CACHE.L3.LOAD.MPKI.SPEC |The rate of speculative L3 cache misses caused by data loads per kilo instructions retired |CACHE.L3.LOAD.MISS.SPEC / RETIRED.INST * 1000
|CACHE.L3.LOAD.MISS.RATE.SPEC |The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data loads |CACHE.L3.LOAD.MISS.SPEC / CACHE.L3.LOAD.ACCESS.SPEC
|CACHE.L3.STORE.MPKI.SPEC |The rate of speculative L3 cache misses caused by data stores per kilo instructions retired |CACHE.L3.STORE.MISS.SPEC / RETIRED.INST * 1000
|CACHE.L3.STORE.MISS.RATE.SPEC |The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data stores |CACHE.L3.STORE.MISS.SPEC / CACHE.L3.STORE.ACCESS.SPEC
|CACHE.L3.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L3 to next level cache per kilo instructions retired |CACHE.L3.PREF.ISSUED / RETIRED.INST * 1000
|CACHE.L3.PREF.MPKI |The rate of L3 cache misses caused by prefetcher per kilo instructions retired |CACHE.L3.PREF.MISS / RETIRED.INST * 1000
|CACHE.L3.LOAD.SPEC.MPKI |The rate of speculative L3 cache misses caused by data loads per kilo instructions retired |CACHE.L3.LOAD.MISS.SPEC / INST.RET * 1000
|CACHE.L3.LOAD.MISS.SPEC.RATE |The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data loads |CACHE.L3.LOAD.MISS.SPEC / CACHE.L3.LOAD.ACCESS.SPEC
|CACHE.L3.STORE.SPEC.MPKI |The rate of speculative L3 cache misses caused by data stores per kilo instructions retired |CACHE.L3.STORE.MISS.SPEC / INST.RET * 1000
|CACHE.L3.STORE.MISS.SPEC.RATE |The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data stores |CACHE.L3.STORE.MISS.SPEC / CACHE.L3.STORE.ACCESS.SPEC
|CACHE.L3.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L3 to next level cache per kilo instructions retired |CACHE.L3.PREF.ISSUED / INST.RET * 1000
|CACHE.L3.PREF.MPKI |The rate of L3 cache misses caused by prefetcher per kilo instructions retired |CACHE.L3.PREF.MISS / INST.RET * 1000
|CACHE.L3.PREF.UNUSED.RATE |The ratio of unused cachelines brought into L3 by prefetcher to the total number of prefetcher requests issued by L3 |CACHE.L3.PREF.UNUSED / CACHE.L3.PREF.ISSUED
|===

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