Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

serial: implement receive FIFO flush via FCR #103

Open
wants to merge 2 commits into
base: main
Choose a base branch
from
+46 −1
Open

serial: implement receive FIFO flush via FCR #103

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
a1a9b1d
serial: implement receive FIFO flush via FCR
00xc Oct 7, 2024
2e6768d
serial: add a test for receive FIFO flushing
00xc Oct 7, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 7 additions & 0 deletions vm-superio/CHANGELOG.md
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,12 @@
# Changelog

# Upcoming version

## Changed

- Implemented receive FIFO flushing via the FCR register for the `Serial`
device ([#83](https://github.com/rust-vmm/vm-superio/issues/83)).

# v0.8.0

## Changed
Expand Down
40 changes: 39 additions & 1 deletion vm-superio/src/serial.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@ use crate::Trigger;
const DATA_OFFSET: u8 = 0;
const IER_OFFSET: u8 = 1;
const IIR_OFFSET: u8 = 2;
const FCR_OFFSET: u8 = IIR_OFFSET;
const LCR_OFFSET: u8 = 3;
const MCR_OFFSET: u8 = 4;
const LSR_OFFSET: u8 = 5;
Expand All @@ -50,6 +51,8 @@ const IIR_NONE_BIT: u8 = 0b0000_0001;
const IIR_THR_EMPTY_BIT: u8 = 0b0000_0010;
const IIR_RDA_BIT: u8 = 0b0000_0100;

const FCR_FLUSH_IN_BIT: u8 = 0b0000_0010;

const LCR_DLAB_BIT: u8 = 0b1000_0000;

const LSR_DATA_READY_BIT: u8 = 0b0000_0001;
Expand Down Expand Up @@ -625,7 +628,14 @@ impl<T: Trigger, EV: SerialEvents, W: Write> Serial<T, EV, W> {
LCR_OFFSET => self.line_control = value,
MCR_OFFSET => self.modem_control = value,
SCR_OFFSET => self.scratch = value,
// We are not interested in writing to other offsets (such as FCR offset).
FCR_OFFSET => {
// Clear the receive FIFO
if value & FCR_FLUSH_IN_BIT != 0 {
self.in_buffer.clear();
self.clear_lsr_rda_bit();
self.events.in_buffer_empty();
}
}
_ => {}
}
Ok(())
Expand Down Expand Up @@ -824,6 +834,34 @@ mod tests {
assert_eq!(serial.writer().as_slice(), &RAW_INPUT_BUF);
}

#[test]
fn test_serial_rx_flush() {
let intr_evt = EventFd::new(libc::EFD_NONBLOCK).unwrap();
let mut serial = Serial::with_events(intr_evt, ExampleSerialEvents::new(), Vec::new());

// No data yet
let mut lsr = serial.read(LSR_OFFSET);
assert_eq!(lsr & LSR_DATA_READY_BIT, 0);
assert_eq!(serial.fifo_capacity(), FIFO_SIZE);

// Write some bytes and check data is ready
serial.enqueue_raw_bytes(&RAW_INPUT_BUF).unwrap();
lsr = serial.read(LSR_OFFSET);
assert_eq!(lsr & LSR_DATA_READY_BIT, 1);
assert!(serial.fifo_capacity() != FIFO_SIZE);

// Flush the FIFO
serial.write(FCR_OFFSET, FCR_FLUSH_IN_BIT).unwrap();

// No data again
lsr = serial.read(LSR_OFFSET);
assert_eq!(lsr & LSR_DATA_READY_BIT, 0);
assert_eq!(serial.fifo_capacity(), FIFO_SIZE);

// An event should have triggered
assert_eq!(serial.events.buffer_ready_event.read().unwrap(), 1);
}

#[test]
fn test_serial_raw_input() {
let intr_evt = EventFd::new(libc::EFD_NONBLOCK).unwrap();
Expand Down