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Merge pull request #405 from slaclab/app_timing_clksrc
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App timing clksrc (breaks AppTop/AppCore interface when upgrading)
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@ruck314
ruck314 authored Mar 1, 2024
2 parents a0adc82 + 3ba6e5c commit 79efb06
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Showing 3 changed files with 80 additions and 43 deletions.
60 changes: 39 additions & 21 deletions AppTop/rtl/xcku040/AppTop.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -188,6 +188,12 @@ architecture mapping of AppTop is
signal jesdRxSync : slv(1 downto 0);
signal jesdTxSync : Slv7Array(1 downto 0);

signal appTimingClk : sl;
signal appTimingRst : sl;

signal timingClkb : sl;
signal timingRstb : sl;

signal adcValids : Slv7Array(1 downto 0);
signal adcValues : sampleDataVectorArray(1 downto 0, 6 downto 0);

Expand Down Expand Up @@ -215,49 +221,57 @@ begin
(TIMING_BUS_DOMAIN_G = "JESD_2xCLK1") or
(TIMING_BUS_DOMAIN_G = "JESD_UsrCLK0") or
(TIMING_BUS_DOMAIN_G = "JESD_UsrCLK1") or
(TIMING_BUS_DOMAIN_G = "AXI_LITE"))
report "TIMING_BUS_DOMAIN_G be either [REC_CLK,AXI_LITE,JESD_CLK0,JESD_CLK1,JESD_2xCLK0,JESD_2xCLK1,JESD_UsrCLK0,JESD_UsrCLK1]" severity error;
(TIMING_BUS_DOMAIN_G = "AXI_LITE") or
(TIMING_BUS_DOMAIN_G = "APP_CLK"))
report "TIMING_BUS_DOMAIN_G be either [REC_CLK,AXI_LITE,APP_CLK,JESD_CLK0,JESD_CLK1,JESD_2xCLK0,JESD_2xCLK1,JESD_UsrCLK0,JESD_UsrCLK1]" severity error;

timingClk <= timingClkb;
timingRst <= timingRstb;

--------------------------
-- Clock and reset mapping
--------------------------
process(axilClk, axilRst, jesdClk, jesdClk2x, jesdRst, jesdRst2x,
jesdUsrClk, jesdUsrRst, recTimingClk, recTimingRst)
jesdUsrClk, jesdUsrRst, recTimingClk, recTimingRst, appTimingClk, appTimingRst)
begin
case TIMING_BUS_DOMAIN_G is
------------------------------
when "REC_CLK" =>
timingClk <= recTimingClk;
timingRst <= recTimingRst;
timingClkb <= recTimingClk;
timingRstb <= recTimingRst;
------------------------------
when "APP_CLK" =>
timingClkb <= appTimingClk;
timingRstb <= appTimingRst;
------------------------------
when "JESD_CLK0" =>
timingClk <= jesdClk(0);
timingRst <= jesdRst(0);
timingClkb <= jesdClk(0);
timingRstb <= jesdRst(0);
------------------------------
when "JESD_CLK1" =>
timingClk <= jesdClk(1);
timingRst <= jesdRst(1);
timingClkb <= jesdClk(1);
timingRstb <= jesdRst(1);
------------------------------
when "JESD_2xCLK0" =>
timingClk <= jesdClk2x(0);
timingRst <= jesdRst2x(0);
timingClkb <= jesdClk2x(0);
timingRstb <= jesdRst2x(0);
------------------------------
when "JESD_2xCLK1" =>
timingClk <= jesdClk2x(1);
timingRst <= jesdRst2x(1);
timingClkb <= jesdClk2x(1);
timingRstb <= jesdRst2x(1);
------------------------------
when "JESD_UsrCLK0" =>
timingClk <= jesdUsrClk(0);
timingRst <= jesdUsrRst(0);
timingClkb <= jesdUsrClk(0);
timingRstb <= jesdUsrRst(0);
------------------------------
when "JESD_UsrCLK1" =>
timingClk <= jesdUsrClk(1);
timingRst <= jesdUsrRst(1);
timingClkb <= jesdUsrClk(1);
timingRstb <= jesdUsrRst(1);
------------------------------
when others =>
-- (TIMING_BUS_DOMAIN_G = "AXI-LITE")
timingClk <= axilClk;
timingRst <= axilRst;
timingClkb <= axilClk;
timingRstb <= axilRst;
------------------------------
end case;
end process;
Expand Down Expand Up @@ -488,6 +502,8 @@ begin
jesdRst2x => jesdRst2x,
jesdUsrClk => jesdUsrClk,
jesdUsrRst => jesdUsrRst,
appTimingClk => appTimingClk,
appTimingRst => appTimingRst,
-- DaqMux/Trig Interface (timingClk domain)
freezeHw => freezeHw,
timingTrig => timingTrig,
Expand Down Expand Up @@ -523,8 +539,10 @@ begin
-- Top Level Interface
----------------------
-- Timing Interface (timingClk domain)
timingClk => recTimingClk,
timingRst => recTimingRst,
recTimingClk => recTimingClk,
recTimingRst => recTimingRst,
timingClk => timingClkb,
timingRst => timingRstb,
timingBus => timingBus,
timingPhy => timingPhy,
timingPhyClk => timingPhyClk,
Expand Down
60 changes: 39 additions & 21 deletions AppTop/rtl/xcku060/AppTop.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -188,6 +188,12 @@ architecture mapping of AppTop is
signal jesdRxSync : slv(1 downto 0);
signal jesdTxSync : Slv10Array(1 downto 0);

signal appTimingClk : sl;
signal appTimingRst : sl;

signal timingClkb : sl;
signal timingRstb : sl;

signal adcValids : Slv10Array(1 downto 0);
signal adcValues : sampleDataVectorArray(1 downto 0, 9 downto 0);

Expand Down Expand Up @@ -215,49 +221,57 @@ begin
(TIMING_BUS_DOMAIN_G = "JESD_2xCLK1") or
(TIMING_BUS_DOMAIN_G = "JESD_UsrCLK0") or
(TIMING_BUS_DOMAIN_G = "JESD_UsrCLK1") or
(TIMING_BUS_DOMAIN_G = "AXI_LITE"))
report "TIMING_BUS_DOMAIN_G be either [REC_CLK,AXI_LITE,JESD_CLK0,JESD_CLK1,JESD_2xCLK0,JESD_2xCLK1,JESD_UsrCLK0,JESD_UsrCLK1]" severity error;
(TIMING_BUS_DOMAIN_G = "AXI_LITE") or
(TIMING_BUS_DOMAIN_G = "APP_CLK"))
report "TIMING_BUS_DOMAIN_G be either [REC_CLK,AXI_LITE,APP_CLK,,JESD_CLK0,JESD_CLK1,JESD_2xCLK0,JESD_2xCLK1,JESD_UsrCLK0,JESD_UsrCLK1]" severity error;

timingClk <= timingClkb;
timingRst <= timingRstb;

--------------------------
-- Clock and reset mapping
--------------------------
process(axilClk, axilRst, jesdClk, jesdClk2x, jesdRst, jesdRst2x,
jesdUsrClk, jesdUsrRst, recTimingClk, recTimingRst)
jesdUsrClk, jesdUsrRst, recTimingClk, recTimingRst, appTimingClk, appTimingRst)
begin
case TIMING_BUS_DOMAIN_G is
------------------------------
when "REC_CLK" =>
timingClk <= recTimingClk;
timingRst <= recTimingRst;
timingClkb <= recTimingClk;
timingRstb <= recTimingRst;
------------------------------
when "APP_CLK" =>
timingClkb <= appTimingClk;
timingRstb <= appTimingRst;
------------------------------
when "JESD_CLK0" =>
timingClk <= jesdClk(0);
timingRst <= jesdRst(0);
timingClkb <= jesdClk(0);
timingRstb <= jesdRst(0);
------------------------------
when "JESD_CLK1" =>
timingClk <= jesdClk(1);
timingRst <= jesdRst(1);
timingClkb <= jesdClk(1);
timingRstb <= jesdRst(1);
------------------------------
when "JESD_2xCLK0" =>
timingClk <= jesdClk2x(0);
timingRst <= jesdRst2x(0);
timingClkb <= jesdClk2x(0);
timingRstb <= jesdRst2x(0);
------------------------------
when "JESD_2xCLK1" =>
timingClk <= jesdClk2x(1);
timingRst <= jesdRst2x(1);
timingClkb <= jesdClk2x(1);
timingRstb <= jesdRst2x(1);
------------------------------
when "JESD_UsrCLK0" =>
timingClk <= jesdUsrClk(0);
timingRst <= jesdUsrRst(0);
timingClkb <= jesdUsrClk(0);
timingRstb <= jesdUsrRst(0);
------------------------------
when "JESD_UsrCLK1" =>
timingClk <= jesdUsrClk(1);
timingRst <= jesdUsrRst(1);
timingClkb <= jesdUsrClk(1);
timingRstb <= jesdUsrRst(1);
------------------------------
when others =>
-- (TIMING_BUS_DOMAIN_G = "AXI-LITE")
timingClk <= axilClk;
timingRst <= axilRst;
timingClkb <= axilClk;
timingRstb <= axilRst;
------------------------------
end case;
end process;
Expand Down Expand Up @@ -506,6 +520,8 @@ begin
jesdRst2x => jesdRst2x,
jesdUsrClk => jesdUsrClk,
jesdUsrRst => jesdUsrRst,
appTimingClk => appTimingClk,
appTimingRst => appTimingRst,
-- DaqMux/Trig Interface (timingClk domain)
freezeHw => freezeHw,
timingTrig => timingTrig,
Expand Down Expand Up @@ -541,8 +557,10 @@ begin
-- Top Level Interface
----------------------
-- Timing Interface (timingClk domain)
timingClk => recTimingClk,
timingRst => recTimingRst,
recTimingClk => recTimingClk,
recTimingRst => recTimingRst,
timingClk => timingClkb,
timingRst => timingRstb,
timingBus => timingBus,
timingPhy => timingPhy,
timingPhyClk => timingPhyClk,
Expand Down
3 changes: 2 additions & 1 deletion AppTop/ruckus.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,8 @@ loadSource -lib amc_carrier_core -dir "$::DIR_PATH/rtl"
loadSource -lib amc_carrier_core -sim_only -dir "$::DIR_PATH/tb/"

# Check for valid FPGA
if { $::env(PRJ_PART) == "XCKU040-FFVA1156-2-E" } {
if { $::env(PRJ_PART) == "XCKU040-FFVA1156-2-E" ||
$::env(USE_APPTOP_040_INTF) == 1 } {
loadConstraints -path "$::DIR_PATH/xdc/AppTop_gen1.xdc"

if { [info exists ::env(APP_MPS_LNODE)] != 1 || $::env(APP_MPS_LNODE) == 0 } {
Expand Down

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