Merge branch 'xci-option' into gtrxaligncheck-dev

.github/workflows/timing_ci.yml

@@ -60,89 +60,24 @@ jobs:
           github_token: ${{ secrets.GH_TOKEN }}
           publish_dir: doxygen/html
 
+# ----------------------------------------------------------------------------
+
   gen_release:
-    name: Generate Release
-    runs-on: ubuntu-20.04
     needs: [test_and_document]
-    if: startsWith(github.ref, 'refs/tags/')
-    steps:
-
-      - uses: actions/checkout@v2
-        with:
-          fetch-depth: 0
-
-      - uses: actions/setup-python@v2
-        with:
-          python-version: 3.8
-
-      - name: Get Image Information
-        id: get_image_info
-        run: |
-          echo ::set-output name=tag::`git describe --tags`
+    uses: slaclab/ruckus/.github/workflows/gen_release.yml@main
+    with:
+      version: '1.0.0'
+    secrets:
+      GH_TOKEN: ${{ secrets.GH_TOKEN }}
 
-      - name: Get Ruckus
-        run: |
-          git clone https://github.com/slaclab/ruckus.git
-          python -m pip install --upgrade pip
-          pip install -r ruckus/scripts/pip_requirements.txt
-
-      - name: Gen Release
-        env:
-          TRAVIS_REPO_SLUG: ${{ github.repository }}
-          TRAVIS_TAG: ${{ steps.get_image_info.outputs.tag }}
-          GH_REPO_TOKEN: ${{ secrets.GH_TOKEN }}
-        run: |
-          python ruckus/scripts/releaseGen.py
+# ----------------------------------------------------------------------------
 
-  conda_build:
-    name: Anaconda Build
+  conda_build_lib:
     needs: [test_and_document]
-    if: startsWith(github.ref, 'refs/tags/')
-    strategy:
-      matrix:
-        os:
-          - ubuntu-20.04
-    runs-on: ${{ matrix.os }}
-    steps:
-
-      # This step checks out a copy of your repository.
-      - uses: actions/checkout@v2
-        with:
-          fetch-depth: 0
-
-      - uses: actions/setup-python@v2
-        with:
-          python-version: 3.8
-
-      - name: Setup anaconda
-        env:
-          OS_NAME: ${{ matrix.os }}
-        run: |
-          cd ${HOME}
-          wget -O miniconda.sh https://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh
-          bash miniconda.sh -b -p ${HOME}/miniconda
-          export PATH="${HOME}/miniconda/bin:$PATH"
-          source ${HOME}/miniconda/etc/profile.d/conda.sh
-          conda config --set always_yes yes
-          conda config --set channel_priority strict
-          conda install -n base conda-libmamba-solver
-          conda config --set solver libmamba
-          conda install conda-build anaconda-client conda-verify
-          conda update -q conda conda-build
-          conda update --all
+    uses: slaclab/ruckus/.github/workflows/conda_build_lib.yml@main
+    with:
+      version: '1.0.0'
+    secrets:
+      CONDA_UPLOAD_TOKEN_TAG: ${{ secrets.CONDA_UPLOAD_TOKEN_TAG }}
 
-      - name: Get Image Information
-        id: get_image_info
-        env:
-          CONDA_UPLOAD_TOKEN_TAG: ${{ secrets.CONDA_UPLOAD_TOKEN_TAG }}
-          OS_NAME: ${{ matrix.os }}
-        run: |
-          echo ::set-output name=token::$CONDA_UPLOAD_TOKEN_TAG
-          echo ::set-output name=os::linux-64
-
-      - name: Build And Upload
-        run: |
-          export PATH="${HOME}/miniconda/bin:$PATH"
-          source ${HOME}/miniconda/etc/profile.d/conda.sh
-          conda build --debug conda-recipe --output-folder bld-dir -c tidair-tag -c tidair-packages -c conda-forge
-          anaconda -t ${{ steps.get_image_info.outputs.token }} upload --force bld-dir/noarch/*.tar.bz2
+# ----------------------------------------------------------------------------

LCLS-II/core/rtl/ClockTime_186MHz.vhd

@@ -22,7 +22,7 @@ use UNISIM.VCOMPONENTS.ALL;
 library surf;
 use surf.StdRtlPkg.all;
 
-entity ClockTime is
+entity ClockTime_186MHz is
    generic (
       TPD_G    : time    := 1 ns);
    port (
@@ -37,10 +37,10 @@ entity ClockTime is
       wrEnB              : in  sl;
       dataO              : out slv(63 downto 0)
       );
-end ClockTime;
+end ClockTime_186MHz;
 
 -- Define architecture for top level module
-architecture ClockTime_186MHz of ClockTime is
+architecture rtl of ClockTime_186MHz is
 
   constant remainder : slv( 4 downto 0)  := slv(conv_unsigned( 5,5));
   constant divisor   : slv( 4 downto 0)  := slv(conv_unsigned(13,5));
@@ -101,4 +101,4 @@ begin
 
   dataO <= dataB;
 
-end ClockTime_186MHz;
+end rtl;

LCLS-II/core/rtl/TPGPkg.vhd

@@ -241,10 +241,11 @@ package TPGPkg is
       -- AC sync from analog or digital AMC
       acMaster           : sl;
       -- Analog lookahead (master) or digital delay (us)
-      acDelay            : slv(14 downto 0);
+      acTS1              : slv(1 downto 0);
+      acPolarity         : sl;
+      acDelay            : slv(12 downto 0);
       inpDelay           : slv(8 downto 0);
       inpDelayLd         : sl;
-      frameDelay         : slv(15 downto 0);
       baseDivisor        : slv(15 downto 0);
       pulseId            : slv(63 downto 0);
       pulseIdWrEn        : sl;
@@ -293,11 +294,12 @@ package TPGPkg is
       txPolarity         => '0',
       baseDivisor        => x"00C8",
       acMaster           => '1',
-      acDelay            => toSlv(100, 15),
+      acTS1              => "00",
+      acPolarity         => '0',
+      acDelay            => toSlv(100, 13),
       --    acDelay           => toSlv(733,15),
       inpDelay           => (others => '0'),
       inpDelayLd         => '0',
-      frameDelay         => x"0000",
       pulseId            => (others => '0'),
       pulseIdWrEn        => '1',
       timeStamp          => (others => '0'),

LCLS-II/core/rtl/TimingGthWrapper.vhd

@@ -25,6 +25,7 @@ entity TimingGthWrapper is
       TPD_G : time := 1 ns);
 
    port (
+      -- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz)
       stableClk : in sl;
 
       gtRefClk : in  sl;

LCLS-II/core/rtl/TimingStreamTx.vhd

@@ -84,9 +84,16 @@ begin
       v := r;
 
       v.dataBuffEn := not r.dataBuffEn;
-      v.dbufData   := D_215_C;
-      v.ecodData   := K_COM_C;
-      v.dataK      := "01";
+
+      if r.dataBuffEn = '1' then
+        v.dbufData   := x"00";
+        v.ecodData   := x"00";
+        v.dataK      := "00";
+      else
+        v.dbufData   := x"00";
+        v.ecodData   := K_COM_C;
+        v.dataK      := "01";
+      end if;
 
       case (r.state) is
         when IDLE_S =>
@@ -97,42 +104,43 @@ begin
             v.dataBuffEn := '0';
             v.pulseId    := pulseId;
             v.eventCodes := eventCodes;
-            v.dataK      := "11";
+            v.dataK(1)   := '1';
             v.dbufData   := K_280_C;
           end if;
         when FRAME_S =>
           if r.wordCount=NDATABUFF_WORDS then
             v.state     := PULSEID_S;
             v.wordCount := (others=>'0');
-            v.dataK      := "11";
+            v.dataK(1)  := '1';
             v.dbufData   := K_281_C;
           elsif r.dataBuffEn='1' then
             v.dbufData  := r.dataBuff(7 downto 0);
             v.dataBuff  := x"00" & r.dataBuff(r.dataBuff'left downto 8);
             v.wordCount := r.wordCount+1;
           end if;
         when PULSEID_S =>
-          v.dataK     := "00";
-          if r.wordCount=toSlv(32,r.wordCount'length) then
-            v.state     := ECODE_S;
-            v.wordCount := (others=>'0');
-            v.ecodData  := x"7D";
-          else
-            v.wordCount := r.wordCount+1;
-            v.pulseId   := r.pulseId(30 downto 0) & '0';
-            if r.pulseId(31)='0' then
-              v.ecodData := x"70";
+          if r.dataBuffEn='1' then
+            if r.wordCount=toSlv(32,r.wordCount'length) then
+              v.state     := ECODE_S;
+              v.wordCount := (others=>'0');
+              v.ecodData  := x"7D";
             else
-              v.ecodData := x"71";
+              v.wordCount := r.wordCount+1;
+              v.pulseId   := r.pulseId(30 downto 0) & '0';
+              if r.pulseId(31)='0' then
+                v.ecodData := x"70";
+              else
+                v.ecodData := x"71";
+              end if;
             end if;
           end if;
         when ECODE_S =>
           if r.wordCount = toSlv(255,r.wordCount'length) then
             v.state := IDLE_S;
-          else
+          elsif r.dataBuffEn = '1' then
             v.wordCount := r.wordCount+1;
             if r.eventCodes(conv_integer(r.wordCount))='1' then
-              v.dataK    := "00";
+              v.dataK(0) := '0';
               v.ecodData := r.wordCount;
             end if;
           end if;

LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd

@@ -44,7 +44,7 @@ entity TimingGthCoreWrapper is
       axilReadSlave   : out AxiLiteReadSlaveType;
       axilWriteMaster : in  AxiLiteWriteMasterType;
       axilWriteSlave  : out AxiLiteWriteSlaveType;
-
+      -- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz)
       stableClk    : in  sl;  -- Unused in GTHE3, but used in GTHE4/GTYE4
       stableRst    : in  sl;  -- Unused in GTHE3, but used in GTHE4/GTYE4
       -- GTH FPGA IO

LCLS-II/gthUltraScale+/ruckus.tcl

@@ -4,11 +4,13 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
 if { $::env(VIVADO_VERSION) >= 2022.2} {
    loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl"
 
-   loadSource -lib lcls_timing_core   -path "$::DIR_PATH/coregen/TimingGth_extref.dcp"
-   #loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"
-
-   loadSource -lib lcls_timing_core   -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp"
-   #loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
+   if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
+       loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"
+       loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
+   } else {
+       loadSource -lib lcls_timing_core   -path "$::DIR_PATH/coregen/TimingGth_extref.dcp"
+       loadSource -lib lcls_timing_core   -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp"
+   }
 } else {
    puts "\n\nWARNING: $::DIR_PATH requires Vivado 2022.2 (or later)\n\n"
 }

LCLS-II/gthUltraScale/rtl/TimingGtCoreWrapper.vhd

@@ -44,7 +44,7 @@ entity TimingGtCoreWrapper is
       axilReadSlave   : out AxiLiteReadSlaveType;
       axilWriteMaster : in  AxiLiteWriteMasterType;
       axilWriteSlave  : out AxiLiteWriteSlaveType;
-
+      -- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz)
       stableClk    : in  sl;  -- Unused in GTHE3, but used in GTHE4/GTYE4
       stableRst    : in  sl;  -- Unused in GTHE3, but used in GTHE4/GTYE4
       -- GTH FPGA IO

LCLS-II/gthUltraScale/ruckus.tcl

@@ -5,11 +5,13 @@ if { $::env(VIVADO_VERSION) >= 2016.4 } {
 
    loadSource -lib lcls_timing_core -dir "$::DIR_PATH/rtl"
 
-   loadSource -lib lcls_timing_core   -path "$::DIR_PATH/coregen/TimingGth_extref.dcp"
-   # loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"
-
-   loadSource -lib lcls_timing_core   -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp"
-   # loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
+   if { [info exists ::env(LCLS_TIMING_XCI)] != 0 && $::env(LCLS_TIMING_XCI) == 1 } {
+       loadIpCore -path "$::DIR_PATH/coregen/TimingGth_extref.xci"
+       loadIpCore -path "$::DIR_PATH/coregen/TimingGth_fixedlat.xci"
+   } else {
+       loadSource -lib lcls_timing_core   -path "$::DIR_PATH/coregen/TimingGth_extref.dcp"
+       loadSource -lib lcls_timing_core   -path "$::DIR_PATH/coregen/TimingGth_fixedlat.dcp"
+   }
 
 } else {
    puts "\n\nWARNING: $::DIR_PATH requires Vivado 2016.4 (or later)\n\n"

LCLS-II/gtx7/rtl/TimingGtCoreWrapper.vhd

@@ -277,7 +277,7 @@ begin
          RX_OS_CFG_G           => "0000010000000",
          RXCDR_CFG_G           => RXCDR_CFG_C,
          RXDFEXYDEN_G          => '1',
-         RX_EQUALIZER_G        => "DFE",
+         RX_EQUALIZER_G        => "LPM",
          RXSLIDE_MODE_G        => "PMA",
          FIXED_COMMA_EN_G      => "0011",
          FIXED_ALIGN_COMMA_0_G => "----------0101111100",  -- Normal Comma

LCLS-II/gtyUltraScale+/rtl/TimingGtCoreWrapper.vhd

@@ -45,7 +45,7 @@ entity TimingGtCoreWrapper is
       axilReadSlave   : out AxiLiteReadSlaveType;
       axilWriteMaster : in  AxiLiteWriteMasterType;
       axilWriteSlave  : out AxiLiteWriteSlaveType;
-
+      -- StableClk (which is GT's drpClk) in the IP core configured for 156.25MHz/2 (78.125MHz)
       stableClk    : in  sl;            -- Unused in GTHE3, but used in GTHE4/GTYE4
       stableRst    : in  sl;            -- Unused in GTHE3, but used in GTHE4/GTYE4
       -- GTY FPGA IO

conda-recipe/build.sh

@@ -1,4 +1,4 @@
 #!/usr/bin/bash
-  
+
 python setup.py install
 

generateDocumentationAndDeploy.sh

@@ -88,7 +88,7 @@ echo "" > .nojekyll
 echo 'Generating Doxygen code documentation...'
 doxygen -v
 
-# Update the INPUT configuration 
+# Update the INPUT configuration
 echo "INPUT = $TRAVIS_BUILD_DIR" >> $DOXYFILE
 
 # # Update the EXCLUDE configuration