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Merge remote-tracking branch 'origin/pre-release' into recclkout-dev
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bengineerd committed Mar 6, 2024
2 parents 0d5b38a + 3b83ea2 commit d8a13ad
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Showing 4 changed files with 5 additions and 5 deletions.
4 changes: 2 additions & 2 deletions LCLS-II/core/rtl/TimingDeserializer.vhd
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Expand Up @@ -79,9 +79,9 @@ architecture TimingDeserializer of TimingDeserializer is
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal crc : slv(31 downto 0);

begin

fiducial <= r.fiducial;
streams <= r.streams;
advance <= r.advance;
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2 changes: 1 addition & 1 deletion LCLS-II/core/rtl/TimingFrameRx.vhd
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Expand Up @@ -83,7 +83,7 @@ architecture rtl of TimingFrameRx is
signal dframe : DataArray;
signal dstrobe : slv(15 downto 1);
signal dvalid : slv(15 downto 1);

begin

delayRst <= rxRst or messageDelayRst or doverflow0;
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2 changes: 1 addition & 1 deletion LCLS-II/core/rtl/TimingRx.vhd
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Expand Up @@ -193,7 +193,7 @@ begin
rxVersion => rxVersion(1),
staData => staData (1));
end generate;

axilComb : process (axilR, axilRst, axilReadMaster, axilRxLinkUp, axilStatusCounters12,
axilStatusCounters3, axilVersion, axilVsnErr, axilWriteMaster, rxStatusCount,
timingTSEvCntGray_o, txClkCntS) is
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2 changes: 1 addition & 1 deletion LCLS-II/gthUltraScale+/rtl/TimingGthCoreWrapper.vhd
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Expand Up @@ -81,7 +81,7 @@ entity TimingGthCoreWrapper is
txOutClk : out sl;

loopback : in slv(2 downto 0));

end entity TimingGthCoreWrapper;

architecture rtl of TimingGthCoreWrapper is
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