added ClockTime ports

[mmishra9]

Added ports: "steps, remainder, divisor" to ClockTime.vhd

[ruck314]

@thatweaver The original defaults for these ports where the following:
https://github.com/slaclab/lcls-timing-core/blob/pre-release/LCLS-II/core/rtl/ClockTime.vhd#L29-L32

      -- Defaults to a step duration of 5-5/13 nanoseconds (1300/7 MHz)
      step               : in slv( 4 downto 0) := slv(conv_unsigned( 5,5));
      remainder          : in slv( FRACTION_DEPTH_G-1 downto 0) := slv(conv_unsigned( 5,FRACTION_DEPTH_G));
      divisor            : in slv( FRACTION_DEPTH_G-1 downto 0) := slv(conv_unsigned(13,FRACTION_DEPTH_G));

In this PR, Mudit changed them to this ...

      step      => toSlv(8,5),
      remainder => toSlv(2,5),
      divisor   => toSlv(5,5),

The step, remainder, and divisor are all now different. Is that going to be a problem?

[thatweaver]

Yes, you're right. Was it necessary to add these extra parameters on the instanciation rather than accept the defaults?

…

-Matt

________________________________ From: Larry Ruckman ***@***.***> Sent: Friday, August 16, 2024 2:28 PM To: slaclab/lcls-timing-core ***@***.***> Cc: Weaver, Matt ***@***.***>; Mention ***@***.***> Subject: Re: [slaclab/lcls-timing-core] added ClockTime ports (PR #169) BEWARE: This email originated outside of our organization. DO NOT CLICK links or attachments unless you recognize the sender and know the content is safe. @thatweaver<https://github.com/thatweaver> The original defaults for these ports where the following: https://github.com/slaclab/lcls-timing-core/blob/pre-release/LCLS-II/core/rtl/ClockTime.vhd#L29-L32

-- Defaults to a step duration of 5-5/13 nanoseconds (1300/7 MHz) step : in slv( 4 downto 0) := slv(conv_unsigned( 5,5)); remainder : in slv( FRACTION_DEPTH_G-1 downto 0) := slv(conv_unsigned( 5,FRACTION_DEPTH_G)); divisor : in slv( FRACTION_DEPTH_G-1 downto 0) := slv(conv_unsigned(13,FRACTION_DEPTH_G)); In this PR, Mudit changed them to this ... step => toSlv(8,5), remainder => toSlv(2,5), divisor => toSlv(5,5), The step and divisor are now different. Is that going to be a problem? — Reply to this email directly, view it on GitHub<#169 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AFC3WOIQZ275THCSPNCBW73ZRZHG3AVCNFSM6AAAAABMQX3PVWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDEOJUGA2TOMJRHE>. You are receiving this because you were mentioned.Message ID: ***@***.***>

[mmishra9]

I looked at these values here:

lcls-timing-core/LCLS-II/core/rtl/TPGMiniStream.vhd

Line 241 in db6464c

U_ClockTime : entity lcls_timing_core.ClockTime

. But it's for a different module, so I probably made a mistake.

I can remove those three ports so that they go to default values if that's correct. Let me know.

[thatweaver]

Yes, please remove. The TPGMiniStream does use values different from the default. The TPGMini.vhd module does not.

…

-Matt

________________________________ From: Mudit Mishra ***@***.***> Sent: Friday, August 16, 2024 2:43 PM To: slaclab/lcls-timing-core ***@***.***> Cc: Weaver, Matt ***@***.***>; Mention ***@***.***> Subject: Re: [slaclab/lcls-timing-core] added ClockTime ports (PR #169) BEWARE: This email originated outside of our organization. DO NOT CLICK links or attachments unless you recognize the sender and know the content is safe. I looked at these values here: https://github.com/slaclab/lcls-timing-core/blob/db6464c3e9b3d4450e2662286bb6d54738222f52/LCLS-II/core/rtl/TPGMiniStream.vhd#L241 . But it's for a different module, so I probably made a mistake. I can remove those three ports so that they go to default values if that's correct. Let me know. — Reply to this email directly, view it on GitHub<#169 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AFC3WOLHBGESO5LJ2LVTANDZRZI53AVCNFSM6AAAAABMQX3PVWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDEOJUGEYDONZZGQ>. You are receiving this because you were mentioned.Message ID: ***@***.***>