Add RowFpgaBoardTb

firmware/common/warm_tdm/sim/CableModel.vhd

@@ -0,0 +1,56 @@
+-------------------------------------------------------------------------------
+-- Title      : 
+-------------------------------------------------------------------------------
+-- Company    : SLAC National Accelerator Laboratory
+-- Platform   : 
+-- Standard   : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: 
+-------------------------------------------------------------------------------
+-- This file is part of Warm TDM. It is subject to
+-- the license terms in the LICENSE.txt file found in the top-level directory
+-- of this distribution and at:
+--    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of Warm TDM, including this file, may be
+-- copied, modified, propagated, or distributed except according to the terms
+-- contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+
+library warm_tdm;
+use warm_tdm.SimPkg.all;
+
+entity CableModel is
+
+   generic (
+      CABLE_R_G : real := 30.0);
+   port (
+      v_in      : in  CurrentType;
+      v_out     : out CurrentType;
+      vload_in  : in  real;
+      vload_out : out real);
+
+
+end entity CableModel;
+
+architecture sim of CableModel is
+
+   signal sumImpedance : real;
+
+begin
+
+   sumImpedance <= vin.impedance + CABLE_R_G;
+
+   -- Add resistance for output
+   v_out <= (voltage => v_in.voltage, impedance => sumImpedance);
+
+   -- Load module returns vload
+   -- Calculate load back to source including cable resistance
+   vload_out <= ((CABLE_R_G*vin.voltage) + (vin.impedance*vload_in)) / (sumImpedance);
+
+end architecture sim;
+

firmware/common/warm_tdm/sim/RowFebFastDacAmp.vhd

@@ -0,0 +1,69 @@
+-------------------------------------------------------------------------------
+-- Title      : 
+-------------------------------------------------------------------------------
+-- Company    : SLAC National Accelerator Laboratory
+-- Platform   : 
+-- Standard   : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: 
+-------------------------------------------------------------------------------
+-- This file is part of Warm TDM. It is subject to
+-- the license terms in the LICENSE.txt file found in the top-level directory
+-- of this distribution and at:
+--    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of Warm TDM, including this file, may be
+-- copied, modified, propagated, or distributed except according to the terms
+-- contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+
+library warm_tdm;
+use warm_tdm.SimPkg.all;
+
+entity RowFebFastDacAmp is
+   generic (
+      IN_LOAD_R_G  : real := 24.9;
+      FB_R_G       : real := 402.0;
+      GAIN_R_G     : real := 100.0;
+      SHUNT_R_G    : real := 1.00e3);
+   port (
+      -- DAC input currents
+      dacP : in real;
+      dacN : in real;
+
+      -- Output currents
+      outP : out CurrentType;
+      outN : out CurrentType);
+
+end entity RowFebFastDacAmp;
+
+architecture sim of RowFebFastDacAmp is
+
+   signal ampInP : real;
+   signal ampInN : real;
+
+   signal ampOutP : real;
+   signal ampOutN : real;
+
+begin
+
+   ampInP <= dacP * IN_LOAD_R_G;
+   ampInN <= dacN * IN_LOAD_R_G;
+
+   ampOutP <= ampInP * (FB_R_G + GAIN_R_G) / GAIN_R_G;
+   ampOutN <= ampInN * (FB_R_G + GAIN_R_G) / GAIN_R_G;
+
+   outP <= (
+      voltage => ampOutP,
+      impedance => 49.9*3 + SHUNT_R_G);
+
+   outN <= (
+      voltage => ampOutN,
+      impedance => 49.9*3 + SHUNT_R_G);
+
+end sim;

firmware/common/warm_tdm/sim/RowFebModel.vhd

@@ -0,0 +1,77 @@
+-------------------------------------------------------------------------------
+-- Title      : Row Readout Front End Board Model
+-------------------------------------------------------------------------------
+-- Company    : SLAC National Accelerator Laboratory
+-- Platform   : 
+-- Standard   : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: 
+-------------------------------------------------------------------------------
+-- This file is part of Warm TDM. It is subject to
+-- the license terms in the LICENSE.txt file found in the top-level directory
+-- of this distribution and at:
+--    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of Warm TDM, including this file, may be
+-- copied, modified, propagated, or distributed except according to the terms
+-- contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+
+library warm_tdm;
+use warm_tdm.SimPkg.all;
+
+entity RowFebModel is
+
+   generic (
+      TPD_G : time := 1 ns);
+
+   port (
+      -- FEB Connector
+      feThermistor : out   slv(1 downto 0) := "00";
+      feI2cScl     : inout slv(3 downto 0);
+      feI2cSda     : inout slv(3 downto 0);
+      resetB       : in    sl;
+      feVrSyncA    : in    sl;
+      feVrSyncB    : in    sl;
+      feDacMosi    : in    sl;
+      feDacMiso    : out   sl;
+      feDacSclk    : in    sl;
+      feDacSyncB   : in    slv(2 downto 0);
+      feDacLdacB   : in    slv(2 downto 0) := (others => '1');
+      feDacResetB  : in    slv(2 downto 0) := (others => '1');
+      tesDelatch   : in    slv(7 downto 0) := (others => '0');
+      rsDacP       : in    RealArray(31 downto 0);
+      rsDacN       : in    RealArray(31 downto 0);
+
+      -- CRYO Connector
+      rsP : out CurrentArray(31 downto 0);
+      rsN : out CurrentArray(31 downto 0));
+
+end entity RowFebModel;
+
+architecture sim of RowFebModel is
+
+
+begin
+
+   GEN_CHANNELS : for i in 31 downto 0 generate
+
+      U_ColumnFebFastDacAmp_SA_FB : entity warm_tdm.RowFebFastDacAmp
+         generic map (
+--             IN_LOAD_R_G => IN_LOAD_R_G,
+--             FB_R_G      => FB_R_G,
+--             GAIN_R_G    => GAIN_R_G,
+            SHUNT_R_G => 1.00e3)
+         port map (
+            dacP => rsDacP(i),          -- [in]
+            dacN => rsDacN(i),          -- [in]
+            outP => rsP(i),             -- [out]
+            outN => rsN(i));            -- [out]
+
+   end generate GEN_CHANNELS;
+
+end architecture sim;