Directly add prefix v into op name for vreinterpret, vsetvl and vse…

…tvlmax intrinsics
tclin914 · Dec 26, 2023 · 305a1dd · 305a1dd
1 parent c6683ec
commit 305a1dd
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Showing 3 changed files with 3 additions and 11 deletions.
diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/inst.py
@@ -477,14 +477,14 @@ def gen(g):
   g.start_group("Miscellaneous Vector Utility Intrinsics")
 
   g.function_group(setvl_template, "Get `vl` with specific vtype",
-                   "set-vl-and-vtype", ["setvl"], [], SEWS, LMULS, [])
+                   "set-vl-and-vtype", ["vsetvl"], [], SEWS, LMULS, [])
 
   g.function_group(setvl_template, "Get `VLMAX` with specific vtype",
-                   "set-vl-to-vlmax-with-specific-vtype", ["setvlmax"], [],
+                   "set-vl-to-vlmax-with-specific-vtype", ["vsetvlmax"], [],
                    SEWS, LMULS, [])
 
   g.function_group(reint_op_template, "Reinterpret Cast Conversion Intrinsics",
-                   "reinterpret-cast-conversion", ["reinterpret"], "", SEWS,
+                   "reinterpret-cast-conversion", ["vreinterpret"], "", SEWS,
                    LMULS, decorators.has_no_masking)
 
   g.function_group(misc_op_template, "Vector LMUL Extension Intrinsics",

diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/reint_op_template.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/reint_op_template.py
@@ -63,8 +63,6 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list):
       if not type_helper.valid_vtype(rt):
         continue
 
-      args["OP"] = "v" + args["OP"]
-
       func_name =\
         "{OP}_v_{TYPES3}{SEW}m{LMUL}_{TYPES1}{SEW}m{LMUL}".format_map(args)
       src_type = "v{TYPES2}{SEW}m{LMUL}_t".format_map(args)
@@ -101,8 +99,6 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list):
       if not type_helper.valid_vtype(rt):
         continue
 
-      args["OP"] = "v" + args["OP"]
-
       func_name =\
         "{OP}_v_{TYPES3}{SEW}m{LMUL}_{TYPES1}{DST_SEW}m{LMUL}".format_map(args)
       src_type = "v{TYPES2}{SEW}m{LMUL}_t".format_map(args)
@@ -125,8 +121,6 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list):
     for args in prod(
         OP=op_list, SEW=sew_list, TYPES=convert_set, LMUL=lmul_list):
 
-      args["OP"] = "v" + args["OP"]
-
       type_helper = TypeHelper(**args)
       args["TYPES0"] = args["TYPES"][0]
       args["TYPES1"] = args["TYPES"][1]

diff --git a/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/setvl_template.py b/rvv-intrinsic-generator/rvv_intrinsic_gen/templates/setvl_template.py
@@ -32,8 +32,6 @@ def render(G, op_list, type_list, sew_list, lmul_list, decorator_list):
   # interface consistency. We can prune it in the future.
   G.inst_group_prologue()
   for args in prod(OP=op_list, SEW=sew_list, LMUL=lmul_list):
-    args["OP"] = "v" + args["OP"]
-
     type_helper = TypeHelper(**args)
 
     if args["OP"] == "vsetvlmax":