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Mcm.cpp
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#include <iostream>
#include <string_view>
#include "Mcm.hpp"
#include "System.hpp"
#include "Hart.hpp"
using namespace WdRiscv;
using std::cerr;
template <typename URV>
Mcm<URV>::Mcm(unsigned hartCount, unsigned pageSize, unsigned mergeBufferSize)
: pageSize_(pageSize), lineSize_(mergeBufferSize)
{
sysMemOps_.reserve(200000);
hartData_.resize(hartCount);
for (auto& hd : hartData_)
{
hd.instrVec_.resize(200000);
hd.regTime_.resize(totalRegCount_);
hd.regProducer_.resize(totalRegCount_);
}
// If no merge buffer, then memory is updated on insert messages.
writeOnInsert_ = (lineSize_ == 0);
// Enable all rules.
ppoEnabled_.resize(PpoRule::Limit, true);
// Currently Io PPO is disabled by default.
ppoEnabled_.at(unsigned(PpoRule::Io)) = false;
}
template <typename URV>
Mcm<URV>::~Mcm() = default;
template <typename URV>
inline
bool
Mcm<URV>::updateTime(const char* method, uint64_t time)
{
if (time < time_)
{
cerr << "Warning: " << method << ": Backward time: "
<< time << " < " << time_ << "\n";
return true;
}
time_ = time;
return true;
}
template <typename URV>
bool
Mcm<URV>::referenceModelRead(Hart<URV>& hart, uint64_t pa, unsigned size, uint64_t& data)
{
data = 0;
bool isDevice = hart.isAclintMtimeAddr(pa) or hart.isImsicAddr(pa) or hart.isPciAddr(pa);
if (isDevice)
{
hart.deviceRead(pa, size, data);
return true;
}
if (uint64_t toHost = 0; hart.getToHostAddress(toHost) && toHost == pa)
return true; // Reading from toHost yields 0.
bool ok = true;
if (size == 1)
{
uint8_t val = 0;
ok = hart.peekMemory(pa, val, true /*usePma*/);
data = val;
}
else if (size == 2)
{
uint16_t val = 0;
ok = hart.peekMemory(pa, val, true /*usePma*/);
data = val;
}
else if (size == 4)
{
uint32_t val = 0;
ok = hart.peekMemory(pa, val, true /*usePma*/);
data = val;
}
else if (size == 8)
{
uint64_t val = 0;
ok = hart.peekMemory(pa, val, true /*usePma*/);
data = val;
}
else if (size < 8)
{
uint8_t val = 0;
for (unsigned i = 0; i < size; ++i)
if (not hart.peekMemory(pa + i, val, true))
{
ok = false;
break;
}
else
data = data | (uint64_t(val) << (8*i));
}
else
assert(0 && "invalid mcm-read size");
return ok;
}
template <typename URV>
bool
Mcm<URV>::readOp(Hart<URV>& hart, uint64_t time, uint64_t tag, uint64_t pa, unsigned size,
uint64_t rtlData, unsigned elemIx, unsigned field)
{
if (not updateTime("Mcm::readOp", time))
return false;
if (size == 0 or size > 8)
{
cerr << "Error: Mcm::readOp: hart-id=" << hart.hartId() << " time=" << time
<< " tag=" << tag << " invalid read size: " << size << '\n';
return false;
}
// Split in two ops Crossing a line boundary to avoid being too pessimistic
// when checking for overlap with stores from other harts
if (lineNum(pa) != lineNum(pa + size - 1))
{
unsigned size1 = offsetToNextLine(pa);
unsigned size2 = size - size1;
uint64_t pa2 = pa + size1;
uint64_t rtlData1 = rtlData & ((uint64_t(1) << (size1*8)) - 1);
uint64_t rtlData2 = rtlData >> (size1*8);
bool ok = readOp_(hart, time, tag, pa, size1, rtlData1, elemIx, field);
ok = readOp_(hart, time, tag, pa2, size2, rtlData2, elemIx, field) and ok;
return ok;
}
return readOp_(hart, time, tag, pa, size, rtlData, elemIx, field);
}
template <typename URV>
bool
Mcm<URV>::readOp_(Hart<URV>& hart, uint64_t time, uint64_t tag, uint64_t pa, unsigned size,
uint64_t rtlData, unsigned elemIx, unsigned field)
{
unsigned hartIx = hart.sysHartIndex();
McmInstr* instr = findOrAddInstr(hartIx, tag);
if (instr->isCanceled())
return true;
if (instr->isRetired() and not hart.getPma(pa).isIo())
cerr << "Warning: hart-id=" << hart.hartId() << " time=" << time <<
" tag=" << tag << " read-op seen after instruction retires\n";
MemoryOp op = {};
op.time_ = time;
op.pa_ = pa;
op.rtlData_ = rtlData;
op.tag_ = tag;
op.hartIx_ = hartIx;
op.size_ = size;
op.isRead_ = true;
op.canceled_ = true; // To be later marked as false if used.
op.elemIx_ = elemIx;
op.field_ = field;
op.isIo_ = hart.getPma(op.pa_).isIo();
assert(pageNum(pa) == pageNum(pa + size - 1));
instr->isLoad_ = true;
// Read Whisper memory and keep it in op, this will be updated when the load is retired
// by forwarding from preceding stores.
uint64_t refVal = 0;
if (referenceModelRead(hart, pa, size, refVal))
op.data_ = refVal;
else
op.failRead_ = true;
if (sysMemOps_.empty() or sysMemOps_.back().time_ <= time)
{
instr->addMemOp(sysMemOps_.size());
sysMemOps_.push_back(op);
}
else
{
// Sometimes the test-bench will unexpectedly send us a read-op with an out of order
// time-stamp. We hack a repair.
// Find first existing op with time > current time.
auto iter = std::upper_bound(sysMemOps_.begin(), sysMemOps_.end(), time,
[](const uint64_t& t, const MemoryOp& mop) -> bool
{ return t < mop.time_; });
// Insert new op before the found op.
assert(iter != sysMemOps_.end());
size_t ix = iter - sysMemOps_.begin();
instr->addMemOp(ix);
sysMemOps_.insert(iter, op);
// Adjust indices of all the instructions referencing ops that are now after new op
// in sysMemOps_.
// One set of adjusted tags per hart.
std::vector< std::unordered_set<uint64_t> > adjustedTags(hartData_.size());
for (size_t i = ix + 1; i < sysMemOps_.size(); ++i)
{
auto& movedOp = sysMemOps_.at(i);
auto& instrVec = hartData_.at(movedOp.hartIx_).instrVec_;
auto& tagSet = adjustedTags.at(movedOp.hartIx_);
auto tag = movedOp.tag_;
if (tagSet.contains(tag))
continue;
tagSet.insert(tag);
auto& instr = instrVec.at(tag);
for (auto& instrOpIx : instr.memOps_)
if (instrOpIx >= ix)
instrOpIx++;
}
}
if (instr->retired_)
instr->complete_ = checkLoadComplete(*instr);
return true;
}
template <typename URV>
McmInstr*
Mcm<URV>::findInstr(unsigned hartIx, uint32_t tag)
{
auto& vec = hartData_.at(hartIx).instrVec_;
if (tag < vec.size() and vec.at(tag).tag_ == tag)
return &(vec.at(tag));
return nullptr;
}
template <typename URV>
McmInstr*
Mcm<URV>::findOrAddInstr(unsigned hartIx, uint32_t tag)
{
auto ptr = findInstr(hartIx, tag);
if (ptr)
return ptr;
auto& vec = hartData_.at(hartIx).instrVec_;
if (tag >= vec.size())
{
if (tag > 500000000)
{
cerr << "MCM: Instruction tag way too large: " << tag << '\n';
cerr << "MCM: Code expects dense consecutive tags starting at 0\n";
assert(0);
}
McmInstr instr;
instr.tag_ = tag;
instr.hartIx_ = hartIx;
vec.resize(tag + 1);
vec.at(tag) = instr;
return &vec.at(tag);
}
if (vec.at(tag).tag_ != 0)
{
cerr << "Mcm::findOrAddInstr: Error: Instr tag already in use\n";
assert(0 && "Mcm::findOrAddInstr: Instr tag already in use");
}
vec.at(tag).tag_ = tag;
vec.at(tag).hartIx_ = hartIx;
return &vec.at(tag);
}
template <typename URV>
void
Mcm<URV>::setBranchMemTime(const Hart<URV>& hart, const McmInstr& instr)
{
const DecodedInst& di = instr.di_;
if (not di.isBranch())
return;
unsigned hartIx = hart.sysHartIndex();
auto& regTimeVec = hartData_.at(hartIx).regTime_;
auto& branchTime = hartData_.at(hartIx).branchTime_;
auto& branchProducer = hartData_.at(hartIx).branchProducer_;
auto& regProducer = hartData_.at(hartIx).regProducer_;
std::vector<unsigned> sourceRegs, destRegs;
identifyRegisters(hart, di, sourceRegs, destRegs);
branchTime = 0;
branchProducer = 0;
if (sourceRegs.empty())
return;
for (auto regIx : sourceRegs)
{
if (regTimeVec.at(regIx) > branchTime)
{
branchTime = regTimeVec.at(regIx);
branchProducer = regProducer.at(regIx);
}
}
}
template <typename URV>
unsigned
Mcm<URV>::getLdStDataVectors(const Hart<URV>& hart, const McmInstr& instr,
std::array<std::pair<unsigned,VecKind>, 32>& vecs) const
{
if (not instr.di_.isVectorLoad() and not instr.di_.isVectorStore())
return 0;
auto& info = hart.getLastVectorMemory();
auto& elems = info.elems_;
unsigned elemSize = info.elemSize_;
assert(elemSize != 0);
unsigned elemsPerVec = hart.vecRegSize() / elemSize;
std::array<bool, 32> referenced; for (auto& x : referenced) x = false;
std::array<bool, 32> active; for (auto& x : active) x = false;
std::array<bool, 32> preserve; for (auto& x : preserve) x = true;
bool maskAgn = hart.isVectorMaskAgnostic();
bool tailAgn = hart.isVectorTailAgnostic();
for (auto& elem : elems)
{
unsigned regNum = info.vec_ + elem.field_*info.group_ + elem.ix_ / elemsPerVec;
referenced.at(regNum) = true; // Vector covers one or more element of instr.
if (elem.skip_)
{
bool masked = elem.ix_ < info.elemCount_;
bool drop = masked ? maskAgn : tailAgn;
preserve.at(regNum) = preserve.at(regNum) and not drop;
}
else
active.at(regNum) = true; // Vector has one or more active element.
}
unsigned count = 0;
for (unsigned regNum = 0; regNum < 32; ++regNum)
if (referenced.at(regNum))
{
VecKind kind = VecKind::Skip;
if (active.at(regNum))
kind = VecKind::Active;
else if (preserve.at(regNum))
kind = VecKind::Preserve;
vecs.at(count++) = std::pair<unsigned, VecKind>{regNum, kind};
}
return count;
}
template <typename URV>
unsigned
Mcm<URV>::getLdStIndexVectors(const Hart<URV>& hart, const McmInstr& instr,
std::array<std::pair<unsigned,VecKind>, 32>& vecs) const
{
if (not instr.di_.isVectorLoad() and not instr.di_.isVectorStore())
return 0;
auto& info = hart.getLastVectorMemory();
if (not info.isIndexed_)
return 0;
auto& elems = info.elems_;
unsigned ixElemSize = hart.vecLdStIndexElemSize(instr.di_);
assert(ixElemSize != 0);
unsigned elemsPerVec = hart.vecRegSize() / ixElemSize;
std::array<bool, 32> referenced; for (auto& x : referenced) x = false;
std::array<bool, 32> active; for (auto& x : active) x = false;
for (auto& elem : elems)
{
unsigned regNum = info.ixVec_ + elem.ix_ / elemsPerVec;
// It's possible tail extends past the number of registers. This is because
// we do not perform a read for indices part of the tail.
if (elem.ix_ >= info.elemCount_)
continue;
if (not elem.skip_)
active.at(regNum) = true;
referenced.at(regNum) = true;
}
unsigned count = 0;
for (unsigned regNum = 0; regNum < 32; ++regNum)
if (referenced.at(regNum))
{
VecKind kind = active.at(regNum)? VecKind::Active : VecKind::Skip;
vecs.at(count++) = std::pair<unsigned, VecKind>{regNum, kind};
}
return count;
}
static bool isUnitStride(const VecLdStInfo& info)
{
if (info.isIndexed_)
return false;
if (not info.isStrided_)
return true;
unsigned nf = info.fields_ == 0 ? 1 : info.fields_;
return nf * info.elemSize_ == info.stride_;
}
template <typename URV>
void
Mcm<URV>::updateVecLoadDependencies(const Hart<URV>& hart, const McmInstr& instr)
{
assert(instr.di_.isVectorLoad());
auto& info = hart.getLastVectorMemory();
auto& elems = info.elems_;
unsigned elemSize = info.elemSize_;
assert(elemSize != 0);
unsigned elemsPerVec = hart.vecRegSize() / elemSize;
bool unitStride = isUnitStride(info);
bool stride0 = info.isStrided_ and info.stride_ == 0 and info.fields_ == 0;
unsigned hartIx = hart.sysHartIndex();
// Initialize producer/time to 0 unless whole vector is preserved.
std::array<std::pair<unsigned, VecKind>, 32> dataRegs;
unsigned count = getLdStDataVectors(hart, instr, dataRegs);
for (unsigned i = 0; i < count; ++i)
{
auto [regNum, kind] = dataRegs.at(i);
if (kind != VecKind::Preserve)
{
setVecRegTime(hartIx, regNum, 0);
setVecRegProducer(hartIx, regNum, 0);
}
}
if (elemSize == 0 or elems.empty())
return; // Should not happen.
for (auto& elem : elems)
{
if (elem.skip_)
continue; // Non active element
uint64_t pa1 = elem.pa_, pa2 = elem.pa2_;
unsigned size = elemSize, size1 = elemSize;
if (pa1 != pa2)
{
size1 = offsetToNextPage(pa1);
assert(size1 > 0 and size1 < 8);
}
unsigned regNum = info.vec_ + elem.field_*info.group_ + elem.ix_ / elemsPerVec;
auto regTime = vecRegTime(hartIx, regNum);
for (unsigned i = 0; i < size; ++i)
{
uint64_t addr = i < size1 ? pa1 + i : pa2 + i - size1;
uint64_t byteTime = 0;
// For strided with stride=0, test-bench sends one read for all indices.
// Don't use element index for that case.
if (unitStride or stride0)
byteTime = latestByteTime(instr, addr);
else
byteTime = latestByteTime(instr, addr, elem.ix_);
regTime = std::max(byteTime, regTime);
}
setVecRegTime(hartIx, regNum, regTime);
McmInstrIx regProd = (regTime == 0)? 0 : instr.tag_;
setVecRegProducer(hartIx, regNum, regProd);
}
}
template <typename URV>
void
Mcm<URV>::updateDependencies(const Hart<URV>& hart, const McmInstr& instr)
{
assert(instr.retired_);
const DecodedInst& di = instr.di_;
assert(di.isValid());
if (di.operandCount() == 0)
return; // No registers.
if (di.isVectorLoad())
{
updateVecLoadDependencies(hart, instr);
return;
}
if ((di.isStore() and not di.isSc()) or di.isVectorStore())
return; // No destination register.
uint64_t time = 0, tag = 0, csrTime = 0, csrTag = 0;
if (di.isSc())
{
if (URV val = 0; hart.peekIntReg(di.op0(), val) and val == 1)
return; // store-conditional failed.
if (instr.memOps_.empty())
time = ~uint64_t(0); // Will be updated when SC drains to memory.
}
if (not instr.memOps_.empty())
{
// At this point only load/amo/sc instructions should have memory ops.
assert(di.isLoad() or di.isAmo() or di.isSc());
for (const auto& opIx : instr.memOps_)
if (opIx < sysMemOps_.size() and sysMemOps_.at(opIx).time_ > time)
time = sysMemOps_.at(opIx).time_;
}
unsigned hartIx = hart.sysHartIndex();
auto& regTimeVec = hartData_.at(hartIx).regTime_;
auto& regProducer = hartData_.at(hartIx).regProducer_;
// Load/amo/sc/branch/mop do not carry dependencies to dest register: Update time of dest.
if (di.isLoad() or di.isAmo() or di.isSc() or di.isBranch() or di.isMop())
{
auto regIx = effectiveRegIx(di, 0);
if (di.ithOperandMode(0) == OperandMode::Write and regIx != 0)
{
regProducer.at(regIx) = instr.tag_;
regTimeVec.at(regIx) = time;
}
return;
}
// Propagate times from source to destination registers.
auto id = di.instId();
bool isVset = (id == InstId::vsetvl or id == InstId::vsetvli or id == InstId::vsetivli);
if (di.isVector() and not isVset)
{
updateVecRegTimes(hart, instr);
return;
}
bool updatesVl = (id == InstId::vsetvl or id == InstId::vsetvli) and (di.op0() or di.op1());
auto& vlTime = hartData_.at(hartIx).vlTime_;
auto& vlProducer = hartData_.at(hartIx).vlProducer_;
std::vector<unsigned> sourceRegs, destRegs;
identifyRegisters(hart, di, sourceRegs, destRegs);
for (auto regIx : sourceRegs)
{
bool isCsr = regIx >= csRegOffset_;
if (isCsr)
{
csrTime = regTimeVec.at(regIx);
csrTag = regProducer.at(regIx);
continue;
}
if (regTimeVec.at(regIx) > time)
{
time = regTimeVec.at(regIx);
tag = regProducer.at(regIx);
}
if (updatesVl and regTimeVec.at(regIx) > vlTime)
{
vlTime = regTimeVec.at(regIx);
vlProducer = regProducer.at(regIx);
}
}
unsigned vlIx = csRegOffset_ + unsigned(CsrNumber::VL);
for (auto regIx : destRegs)
{
if (regIx == 0)
continue; // Destination is X0
if (not instr.di_.isCsr() or regIx >= csRegOffset_)
{ // Non-CSR instruction or destination is a CSR register.
regTimeVec.at(regIx) = time;
regProducer.at(regIx) = tag;
if (regIx == vlIx and time > vlTime)
{
vlTime = time;
vlProducer = tag;
}
}
else
{ // Integer destination register of a CSR instruction.
regTimeVec.at(regIx) = csrTime;
regProducer.at(regIx) = csrTag;
}
}
}
template <typename URV>
void
Mcm<URV>::updateVecRegTimes(const Hart<URV>& hart, const McmInstr& instr)
{
auto& di = instr.di_;
auto opCount = di.operandCount();
if (opCount == 0)
return;
auto id = di.instId();
bool isVset = (id == InstId::vsetvl or id == InstId::vsetvli or id == InstId::vsetivli);
if (isVset)
{
assert(0);
return;
}
auto hartIx = instr.hartIx_;
auto& regProducer = hartData_.at(hartIx).regProducer_;
auto& regTimeVec = hartData_.at(hartIx).regTime_;
uint64_t time = 0, tag = 0;
assert(di.ithOperandMode(0) == OperandMode::Write); // 1st operand must be the destination
if (di.ithOperandType(0) != OperandType::VecReg)
{
// Destination register is scalar: vcpop.m, vfirst.m, vmv.x.s, or vmv.f.s
assert(id == InstId::vcpop_m or id == InstId::vfirst_m or id == InstId::vmv_x_s or
id == InstId::vfmv_f_s);
assert(opCount == 2);
assert(di.ithOperandType(1) == OperandType::VecReg); // 2nd operand must be vec
auto destIx = effectiveRegIx(di, 0);
if (destIx == 0)
return; // Destination is X0
// Get group multiplier of vector register.
unsigned lmul = 1; // vmv instructions ignore LMUL
if (id == InstId::vcpop_m or id == InstId::vfirst_m)
lmul = hart.vecOpEmul(1);
unsigned baseRegIx = effectiveRegIx(di, 1);
for (unsigned i = 0; i < lmul; ++i)
{
unsigned srcIx = baseRegIx + i;
auto srcTime = regTimeVec.at(srcIx);
if (srcTime > time)
{
time = srcTime;
tag = regProducer.at(srcIx);
}
}
regProducer.at(destIx) = tag;
regTimeVec.at(destIx) = time;
return;
}
auto destEmul = hart.vecOpEmul(0);
unsigned baseDestIx = effectiveRegIx(di, 0);
for (unsigned ii = 0; ii < destEmul; ++ii)
{
time = 0;
tag = 0;
auto destIx = baseDestIx + ii;
// Process all source operands.
for (unsigned so = 1; so < opCount; ++so)
{
if (di.ithOperandType(so) == OperandType::Imm)
continue;
assert(di.ithOperandMode(so) == OperandMode::Read);
if (di.ithOperandType(so) != OperandType::VecReg)
{
// Scalar source operand. Affects all vec regs in dest group.
auto srcIx = effectiveRegIx(di, so);
auto srcTime = regTimeVec.at(srcIx);
if (srcTime > time)
{
time = srcTime;
tag = regProducer.at(srcIx);
}
}
else
{
// Vector source operand.
// We propagate times at the vector register level. In the future we will do
// this at the element or at the byte level.
auto baseSrcIx = effectiveRegIx(di, so);
auto srcEmul = hart.vecOpEmul(so);
if (srcEmul <= destEmul)
{
assert((destEmul % srcEmul) == 0);
// Determine number of dest vec regs per source reg
unsigned ndest = destEmul / srcEmul;
auto jj = ii / ndest; // jj is the index of the source vec reg in its group.
auto srcIx = baseSrcIx + jj; // Source vec reg corresponding to dest.
auto srcTime = regTimeVec.at(srcIx);
if (srcTime > time)
{
time = srcTime;
tag = regProducer.at(srcIx);
}
}
else
{
assert((srcEmul % destEmul) == 0);
// Determine number of src vec regs per dest reg.
unsigned nsrc = srcEmul / destEmul;
unsigned jj = ii*nsrc; // jj is the index of a source vec reg in its group
for (unsigned i = 0; i < nsrc; ++i)
{
auto srcIx = baseSrcIx + jj + i;
auto srcTime = regTimeVec.at(srcIx);
if (srcTime > time)
{
time = srcTime;
tag = regProducer.at(srcIx);
}
}
}
}
}
regProducer.at(destIx) = tag;
regTimeVec.at(destIx) = time;
}
}
template <typename URV>
void
Mcm<URV>::setProducerTime(const Hart<URV>& hart, McmInstr& instr)
{
auto& di = instr.di_;
unsigned hartIx = hart.sysHartIndex();
auto& regProducer = hartData_.at(hartIx).regProducer_;
auto& regTime = hartData_.at(hartIx).regTime_;
// Set producer of address register.
if (di.isLoad() or di.isAmo() or di.isStore() or di.isVectorLoad() or di.isVectorStore())
{
unsigned addrReg = effectiveRegIx(di, 1); // Addr reg is operand 1 of instr.
instr.addrProducer_ = regProducer.at(addrReg);
instr.addrTime_ = regTime.at(addrReg);
}
if (di.isVectorLoadStrided() or di.isVectorStoreStrided())
{
unsigned strideReg = effectiveRegIx(di, 2);
uint64_t addrTime = regTime.at(strideReg);
if (addrTime >= instr.addrTime_)
{
instr.addrProducer_ = regProducer.at(strideReg);
instr.addrTime_ = addrTime;
}
}
// Set producer of data register.
if (di.isStore() or di.isAmo())
{
unsigned doi = di.isAmo()? 2 : 0; // Data-register operand index
unsigned dataReg = effectiveRegIx(di, doi); // Data operand may be integer/fp/csr
instr.dataProducer_ = regProducer.at(dataReg);
instr.dataTime_ = regTime.at(dataReg);
}
if (di.isVectorStore())
{
std::array<std::pair<unsigned, VecKind>, 32> dataVecs; // reg-num/masked pairs
unsigned count = getLdStDataVectors(hart, instr, dataVecs);
unsigned active = 0;
for (unsigned i = 0; i < count; ++i)
{
auto [dataReg, kind] = dataVecs.at(i);
if (kind != VecKind::Active)
continue; // Preserve does not apply to store.
auto time = vecRegTime(hartIx, dataReg);
auto producer = vecRegProducer(hartIx, dataReg);
if (time >= instr.dataTime_)
{
instr.dataProducer_ = producer;
instr.dataTime_ = time;
}
instr.vecProdTimes_.at(active++) = McmInstr::VecProdTime{dataReg, producer, time};
}
}
if (di.isVectorLoadIndexed() or di.isVectorStoreIndexed())
{
std::array<std::pair<unsigned, VecKind>, 32> ixRegs; // reg-num/masked pairs
unsigned count = getLdStIndexVectors(hart, instr, ixRegs);
unsigned active = 0;
for (unsigned i = 0; i < count; ++i)
{
auto [ixReg, kind] = ixRegs.at(i);
if (kind != VecKind::Active) // If we preserve data reg, index reg is not used.
continue;
auto time = regTime.at(ixReg);
auto producer = regProducer.at(ixReg);
// We do not update addrProducer_ and addrTime_: those are for the scalar
// address register.
instr.ixProdTimes_.at(active++) = McmInstr::VecProdTime{ixReg, producer, time};
}
}
}
template <typename URV>
static bool
pokeHartMemory(Hart<URV>& hart, uint64_t physAddr, uint64_t data, unsigned size)
{
bool usePma = true;
bool skipFetch = true;
if (size == 1)
return hart.pokeMemory(physAddr, uint8_t(data), usePma, skipFetch);
if (size == 2)
return hart.pokeMemory(physAddr, uint16_t(data), usePma, skipFetch);
if (size == 4)
return hart.pokeMemory(physAddr, uint32_t(data), usePma, skipFetch);
if (size == 8)
return hart.pokeMemory(physAddr, uint64_t(data), usePma, skipFetch);
if (size < 8)
{
for (unsigned i = 0; i < size; ++i)
if (not hart.pokeMemory(physAddr + i, uint8_t(data >> (8*i)), usePma, skipFetch))
return false;
return true;
}
cerr << "MCM pokeHartMemory: " << "Invalid data size (" << size << ")\n";
return false;
}
template <typename URV>
bool
Mcm<URV>::mergeBufferInsert(Hart<URV>& hart, uint64_t time, uint64_t tag, uint64_t pa,
unsigned size, uint64_t rtlData, unsigned elemIx, unsigned field)
{
if (not updateTime("Mcm::mergeBufferInsert", time))
return false;
assert(size <= 8);
unsigned hartIx = hart.sysHartIndex();
MemoryOp op = {};
op.time_ = time;
op.insertTime_ = time;
op.pa_ = pa;
op.rtlData_ = rtlData;
op.tag_ = tag;
op.hartIx_ = hartIx;
op.size_ = size;
op.isRead_ = false;
op.elemIx_ = elemIx;
op.field_ = field;
op.isIo_ = hart.getPma(op.pa_).isIo();
if (not writeOnInsert_)
hartData_.at(hartIx).pendingWrites_.push_back(op);
McmInstr* instr = findOrAddInstr(hartIx, tag);
if (not instr)
{
cerr << "Mcm::MergeBufferInsertScalar: Error: Unknown instr tag\n";
assert(0 && "Mcm::MergeBufferInsertScalar: Unknown instr tag");
return false;
}
auto& undrained = hartData_.at(hartIx).undrainedStores_;
undrained.insert(tag);
bool result = true;
if (writeOnInsert_)
{
// Associate write op with instruction.
instr->addMemOp(sysMemOps_.size());
sysMemOps_.push_back(op);
instr->complete_ = checkStoreComplete(hartIx, *instr);
if (instr->complete_)
{
undrained.erase(tag);
hartData_.at(hartIx).storeInsertCount_.erase(tag);
checkStoreData(hart, *instr);
}
if (not instr->retired_)
{
cerr << "Mcm::MergeBufferInsertScalar: Error: Merge buffer write for a non-retired store\n";
return false;
}
if (isEnabled(PpoRule::R1))
result = ppoRule1(hart, *instr) and result;
if (instr->di_.isAmo() and isEnabled(PpoRule::R3))
result = ppoRule3(hart, *instr) and result;
// We commit the RTL data to memory but we check them against whisper data (in
// checkStoreData). This is simpler than committing part of whisper instruction
// data.
if (not pokeHartMemory(hart, pa, rtlData, op.size_))
result = false;
}
return result;
}
template <typename URV>
bool
Mcm<URV>::bypassOp(Hart<URV>& hart, uint64_t time, uint64_t tag, uint64_t pa,
unsigned size, uint64_t rtlData, unsigned elemIx, unsigned field)
{
if (not updateTime("Mcm::writeOp", time))
return false;
unsigned hartIx = hart.sysHartIndex();
McmInstr* instr = findOrAddInstr(hartIx, tag);
if (not instr)
{
cerr << "Mcm::bypassOp: Error: hart-id=" << hart.hartId() << " time=" << time
<< " tag=" << tag << " unknown instr tag\n";
return false;
}
if (instr->canceled_)
{
cerr << "Mcm::bypassOp: Error: hart-id=" << hart.hartId() << " time=" << time
<< " tag=" << tag << " bypass op with cancelled instruction\n";
return false;
}
auto& undrained = hartData_.at(hartIx).undrainedStores_;
undrained.insert(tag);
bool result = true;
assert(size <= 8);
MemoryOp op = {};
op.time_ = time;