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backend: removes unnecessary ValueDefinition fields #2287

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Jul 10, 2024
Merged

backend: removes unnecessary ValueDefinition fields #2287

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cef1fd7
backend: removes unnecessary ValueDefinition fields
mathetake Jul 10, 2024
d0e377f
fix test
mathetake Jul 10, 2024
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9 changes: 3 additions & 6 deletions internal/engine/wazevo/backend/compiler.go
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Original file line number Diff line number Diff line change
Expand Up @@ -222,14 +222,13 @@ func (c *compiler) assignVirtualRegisters() {
typ := p.Type()
vreg := c.AllocateVReg(typ)
c.ssaValueToVRegs[pid] = vreg
c.ssaValueDefinitions[pid] = SSAValueDefinition{BlockParamValue: p, BlkParamVReg: vreg}
c.ssaValueDefinitions[pid] = SSAValueDefinition{V: p}
c.ssaTypeOfVRegID[vreg.ID()] = p.Type()
}

// Assigns each value to a virtual register produced by instructions.
for cur := blk.Root(); cur != nil; cur = cur.Next() {
r, rs := cur.Returns()
var N int
if r.Valid() {
id := r.ID()
ssaTyp := r.Type()
Expand All @@ -238,11 +237,10 @@ func (c *compiler) assignVirtualRegisters() {
c.ssaValueToVRegs[id] = vReg
c.ssaValueDefinitions[id] = SSAValueDefinition{
Instr: cur,
N: 0,
V: r,
RefCount: refCounts[id].RefCount,
}
c.ssaTypeOfVRegID[vReg.ID()] = ssaTyp
N++
}
for _, r := range rs {
id := r.ID()
Expand All @@ -251,11 +249,10 @@ func (c *compiler) assignVirtualRegisters() {
c.ssaValueToVRegs[id] = vReg
c.ssaValueDefinitions[id] = SSAValueDefinition{
Instr: cur,
N: N,
V: r,
RefCount: refCounts[id].RefCount,
}
c.ssaTypeOfVRegID[vReg.ID()] = ssaTyp
N++
}
}
}
Expand Down
4 changes: 2 additions & 2 deletions internal/engine/wazevo/backend/isa/amd64/lower_mem.go
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Original file line number Diff line number Diff line change
Expand Up @@ -131,8 +131,8 @@ func (m *machine) lowerAddendsToAmode(x, y addend, offBase uint32) *amode {
}

func (m *machine) lowerAddend(x *backend.SSAValueDefinition) addend {
if x.IsFromBlockParam() {
return addend{x.BlkParamVReg, 0, 0}
if !x.IsFromInstr() {
return addend{m.c.VRegOf(x.V), 0, 0}
}
// Ensure the addend is not referenced in multiple places; we will discard nested Iadds.
op := m.c.MatchInstrOneOf(x, addendsMatchOpcodes[:])
Expand Down
33 changes: 22 additions & 11 deletions internal/engine/wazevo/backend/isa/amd64/lower_mem_test.go
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,8 @@ func TestMachine_lowerToAddressMode(t *testing.T) {
ptr = iadd.Return()
offset = 3
ctx.definitions[iconst1.Return()] = &backend.SSAValueDefinition{Instr: iconst1}
ctx.definitions[p] = &backend.SSAValueDefinition{BlockParamValue: p, BlkParamVReg: raxVReg}
ctx.vRegMap[p] = raxVReg
ctx.definitions[p] = &backend.SSAValueDefinition{V: p}
ctx.definitions[ptr] = &backend.SSAValueDefinition{Instr: iadd}
return
},
Expand All @@ -67,8 +68,10 @@ func TestMachine_lowerToAddressMode(t *testing.T) {
iadd := b.AllocateInstruction().AsIadd(p1, p2).Insert(b)
ptr = iadd.Return()
offset = 3
ctx.definitions[p1] = &backend.SSAValueDefinition{BlockParamValue: p1, BlkParamVReg: raxVReg}
ctx.definitions[p2] = &backend.SSAValueDefinition{BlockParamValue: p2, BlkParamVReg: rcxVReg}
ctx.vRegMap[p1] = raxVReg
ctx.definitions[p1] = &backend.SSAValueDefinition{V: p1}
ctx.vRegMap[p2] = rcxVReg
ctx.definitions[p2] = &backend.SSAValueDefinition{V: p2}
ctx.definitions[ptr] = &backend.SSAValueDefinition{Instr: iadd}
return
},
Expand All @@ -79,7 +82,8 @@ func TestMachine_lowerToAddressMode(t *testing.T) {
in: func(ctx *mockCompiler, b ssa.Builder, m *machine) (ptr ssa.Value, offset uint32) {
ptr = b.CurrentBlock().AddParam(b, ssa.TypeI64)
offset = 1 << 31
ctx.definitions[ptr] = &backend.SSAValueDefinition{BlockParamValue: ptr, BlkParamVReg: raxVReg}
ctx.vRegMap[ptr] = raxVReg
ctx.definitions[ptr] = &backend.SSAValueDefinition{V: ptr}
return
},
insts: []string{
Expand Down Expand Up @@ -109,7 +113,8 @@ func TestMachine_lowerToAddressMode(t *testing.T) {
p := b.CurrentBlock().AddParam(b, ssa.TypeI64)
iconst64 := b.AllocateInstruction().AsIconst64(2).Insert(b)
ishl := b.AllocateInstruction().AsIshl(p, iconst64.Return()).Insert(b)
ctx.definitions[p] = &backend.SSAValueDefinition{BlockParamValue: p, BlkParamVReg: raxVReg}
ctx.vRegMap[p] = raxVReg
ctx.definitions[p] = &backend.SSAValueDefinition{V: p}
ctx.definitions[iconst64.Return()] = &backend.SSAValueDefinition{Instr: iconst64}
ctx.definitions[ishl.Return()] = &backend.SSAValueDefinition{Instr: ishl}
return ishl.Return(), 1 << 30
Expand All @@ -127,8 +132,10 @@ func TestMachine_lowerToAddressMode(t *testing.T) {
const2 := b.AllocateInstruction().AsIconst64(2).Insert(b)
ishl := b.AllocateInstruction().AsIshl(p1, const2.Return()).Insert(b)
iadd := b.AllocateInstruction().AsIadd(p2, ishl.Return()).Insert(b)
ctx.definitions[p1] = &backend.SSAValueDefinition{BlockParamValue: p1, BlkParamVReg: raxVReg}
ctx.definitions[p2] = &backend.SSAValueDefinition{BlockParamValue: p2, BlkParamVReg: rcxVReg}
ctx.vRegMap[p1] = raxVReg
ctx.definitions[p1] = &backend.SSAValueDefinition{V: p1}
ctx.vRegMap[p2] = rcxVReg
ctx.definitions[p2] = &backend.SSAValueDefinition{V: p2}
ctx.definitions[const2.Return()] = &backend.SSAValueDefinition{Instr: const2}
ctx.definitions[ishl.Return()] = &backend.SSAValueDefinition{Instr: ishl}
ctx.definitions[iadd.Return()] = &backend.SSAValueDefinition{Instr: iadd}
Expand Down Expand Up @@ -181,7 +188,8 @@ func TestMachine_lowerAddendFromInstr(t *testing.T) {
name: "uextend const64",
in: func(ctx *mockCompiler, b ssa.Builder, m *machine) *ssa.Instruction {
p := b.CurrentBlock().AddParam(b, ssa.TypeI32)
ctx.definitions[p] = &backend.SSAValueDefinition{BlkParamVReg: raxVReg, BlockParamValue: p}
ctx.vRegMap[p] = raxVReg
ctx.definitions[p] = &backend.SSAValueDefinition{V: p}
return b.AllocateInstruction().AsUExtend(p, 32, 64).Insert(b)
},
exp: addend{raxVReg, 0, 0},
Expand All @@ -190,7 +198,8 @@ func TestMachine_lowerAddendFromInstr(t *testing.T) {
name: "uextend param i32",
in: func(ctx *mockCompiler, b ssa.Builder, m *machine) *ssa.Instruction {
p := b.CurrentBlock().AddParam(b, ssa.TypeI32)
ctx.definitions[p] = &backend.SSAValueDefinition{BlkParamVReg: raxVReg, BlockParamValue: p}
ctx.vRegMap[p] = raxVReg
ctx.definitions[p] = &backend.SSAValueDefinition{V: p}
return b.AllocateInstruction().AsUExtend(p, 32, 64).Insert(b)
},
exp: addend{raxVReg, 0, 0},
Expand All @@ -208,7 +217,8 @@ func TestMachine_lowerAddendFromInstr(t *testing.T) {
name: "sextend const64",
in: func(ctx *mockCompiler, b ssa.Builder, m *machine) *ssa.Instruction {
p := b.CurrentBlock().AddParam(b, ssa.TypeI32)
ctx.definitions[p] = &backend.SSAValueDefinition{BlkParamVReg: raxVReg, BlockParamValue: p}
ctx.vRegMap[p] = raxVReg
ctx.definitions[p] = &backend.SSAValueDefinition{V: p}
return b.AllocateInstruction().AsSExtend(p, 32, 64).Insert(b)
},
exp: addend{raxVReg, 0, 0},
Expand All @@ -217,7 +227,8 @@ func TestMachine_lowerAddendFromInstr(t *testing.T) {
name: "sextend param i32",
in: func(ctx *mockCompiler, b ssa.Builder, m *machine) *ssa.Instruction {
p := b.CurrentBlock().AddParam(b, ssa.TypeI32)
ctx.definitions[p] = &backend.SSAValueDefinition{BlkParamVReg: raxVReg, BlockParamValue: p}
ctx.vRegMap[p] = raxVReg
ctx.definitions[p] = &backend.SSAValueDefinition{V: p}
return b.AllocateInstruction().AsSExtend(p, 32, 64).Insert(b)
},
exp: addend{raxVReg, 0, 0},
Expand Down
41 changes: 24 additions & 17 deletions internal/engine/wazevo/backend/isa/amd64/machine_test.go
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Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,8 @@ func TestMachine_getOperand_Reg(t *testing.T) {
{
name: "block param",
setup: func(ctx *mockCompiler, builder ssa.Builder, m *machine) *backend.SSAValueDefinition {
return &backend.SSAValueDefinition{BlkParamVReg: raxVReg, Instr: nil, N: 0}
ctx.vRegMap[1234] = raxVReg
return &backend.SSAValueDefinition{V: 1234, Instr: nil}
},
exp: newOperandReg(raxVReg),
},
Expand All @@ -58,7 +59,7 @@ func TestMachine_getOperand_Reg(t *testing.T) {
instr.AsIconst32(0xf00000f)
builder.InsertInstruction(instr)
ctx.vRegCounter = 99
return &backend.SSAValueDefinition{Instr: instr, N: 0}
return &backend.SSAValueDefinition{Instr: instr}
},
exp: newOperandReg(regalloc.VReg(100).SetRegType(regalloc.RegTypeInt)),
instructions: []string{"movl $251658255, %r100d?"},
Expand All @@ -73,7 +74,7 @@ func TestMachine_getOperand_Reg(t *testing.T) {
builder.InsertInstruction(c)
r := c.Return()
ctx.vRegMap[r] = regalloc.VReg(50)
return &backend.SSAValueDefinition{Instr: c, N: 0}
return &backend.SSAValueDefinition{V: r}
},
exp: newOperandReg(regalloc.VReg(50)),
},
Expand All @@ -87,7 +88,7 @@ func TestMachine_getOperand_Reg(t *testing.T) {
builder.InsertInstruction(c)
_, rs := c.Returns()
ctx.vRegMap[rs[1]] = regalloc.VReg(50)
return &backend.SSAValueDefinition{Instr: c, N: 2}
return &backend.SSAValueDefinition{V: rs[1]}
},
exp: newOperandReg(regalloc.VReg(50)),
},
Expand All @@ -112,7 +113,8 @@ func TestMachine_getOperand_Imm32_Reg(t *testing.T) {
{
name: "block param falls back to getOperand_Reg",
setup: func(ctx *mockCompiler, builder ssa.Builder, m *machine) *backend.SSAValueDefinition {
return &backend.SSAValueDefinition{BlkParamVReg: raxVReg, Instr: nil, N: 0}
ctx.vRegMap[1234] = raxVReg
return &backend.SSAValueDefinition{V: 1234, Instr: nil}
},
exp: newOperandReg(raxVReg),
},
Expand All @@ -124,7 +126,7 @@ func TestMachine_getOperand_Imm32_Reg(t *testing.T) {
builder.InsertInstruction(instr)
ctx.vRegCounter = 99
ctx.currentGID = 0xff // const can be merged anytime, regardless of the group id.
return &backend.SSAValueDefinition{Instr: instr, N: 0}
return &backend.SSAValueDefinition{Instr: instr}
},
exp: newOperandImm32(0xf00000f),
},
Expand Down Expand Up @@ -155,7 +157,8 @@ func Test_machine_getOperand_Mem_Imm32_Reg(t *testing.T) {
{
name: "block param falls back to getOperand_Imm32_Reg",
setup: func(ctx *mockCompiler, builder ssa.Builder, m *machine) *backend.SSAValueDefinition {
return &backend.SSAValueDefinition{BlkParamVReg: raxVReg, Instr: nil, N: 0}
ctx.vRegMap[1234] = raxVReg
return &backend.SSAValueDefinition{V: 1234, Instr: nil}
},
exp: newOperandReg(raxVReg),
},
Expand All @@ -164,10 +167,11 @@ func Test_machine_getOperand_Mem_Imm32_Reg(t *testing.T) {
setup: func(ctx *mockCompiler, builder ssa.Builder, m *machine) *backend.SSAValueDefinition {
blk := builder.CurrentBlock()
ptr := blk.AddParam(builder, ssa.TypeI64)
ctx.definitions[ptr] = &backend.SSAValueDefinition{BlockParamValue: ptr, BlkParamVReg: raxVReg}
ctx.vRegMap[ptr] = raxVReg
ctx.definitions[ptr] = &backend.SSAValueDefinition{V: ptr}
instr := builder.AllocateInstruction()
instr.AsLoad(ptr, 123, ssa.TypeI64).Insert(builder)
return &backend.SSAValueDefinition{Instr: instr, N: 0}
return &backend.SSAValueDefinition{Instr: instr}
},
exp: newOperandMem(newAmodeImmReg(123, raxVReg)),
},
Expand All @@ -178,7 +182,7 @@ func Test_machine_getOperand_Mem_Imm32_Reg(t *testing.T) {
instr := builder.AllocateInstruction()
instr.AsLoad(iconst.Return(), 123, ssa.TypeI64).Insert(builder)
ctx.definitions[iconst.Return()] = &backend.SSAValueDefinition{Instr: iconst}
return &backend.SSAValueDefinition{Instr: instr, N: 0}
return &backend.SSAValueDefinition{Instr: instr}
},
instructions: []string{
"movabsq $579, %r1?", // r1 := 123+456
Expand All @@ -197,7 +201,7 @@ func Test_machine_getOperand_Mem_Imm32_Reg(t *testing.T) {
ctx.definitions[uextend.Return()] = &backend.SSAValueDefinition{Instr: uextend}
ctx.definitions[iconst.Return()] = &backend.SSAValueDefinition{Instr: iconst}

return &backend.SSAValueDefinition{Instr: instr, N: 0}
return &backend.SSAValueDefinition{Instr: instr}
},
instructions: []string{
fmt.Sprintf("movabsq $%d, %%r1?", 0xffffff+123),
Expand All @@ -216,7 +220,7 @@ func Test_machine_getOperand_Mem_Imm32_Reg(t *testing.T) {
ctx.definitions[uextend.Return()] = &backend.SSAValueDefinition{Instr: uextend}
ctx.definitions[iconst.Return()] = &backend.SSAValueDefinition{Instr: iconst}

return &backend.SSAValueDefinition{Instr: instr, N: 0}
return &backend.SSAValueDefinition{Instr: instr}
},
instructions: []string{
fmt.Sprintf("movabsq $%d, %%r1?", 456+123),
Expand All @@ -233,11 +237,12 @@ func Test_machine_getOperand_Mem_Imm32_Reg(t *testing.T) {
instr := builder.AllocateInstruction()
instr.AsLoad(iadd.Return(), 789, ssa.TypeI64).Insert(builder)

ctx.definitions[p] = &backend.SSAValueDefinition{BlockParamValue: p, BlkParamVReg: raxVReg}
ctx.vRegMap[p] = raxVReg
ctx.definitions[p] = &backend.SSAValueDefinition{V: p}
ctx.definitions[iconst.Return()] = &backend.SSAValueDefinition{Instr: iconst}
ctx.definitions[iadd.Return()] = &backend.SSAValueDefinition{Instr: iadd}

return &backend.SSAValueDefinition{Instr: instr, N: 0}
return &backend.SSAValueDefinition{Instr: instr}
},
exp: newOperandMem(newAmodeImmReg(456+789, raxVReg)),
},
Expand All @@ -255,7 +260,7 @@ func Test_machine_getOperand_Mem_Imm32_Reg(t *testing.T) {
ctx.definitions[iconst2.Return()] = &backend.SSAValueDefinition{Instr: iconst2}
ctx.definitions[iadd.Return()] = &backend.SSAValueDefinition{Instr: iadd}

return &backend.SSAValueDefinition{Instr: instr, N: 0}
return &backend.SSAValueDefinition{Instr: instr}
},
instructions: []string{
fmt.Sprintf("movabsq $%d, %%r1?", 123+456+789),
Expand Down Expand Up @@ -361,7 +366,8 @@ L2:
p := b.CurrentBlock().AddParam(b, tc.typ)
m.cpuFeatures = tc.cpuFlags

ctx.definitions[p] = &backend.SSAValueDefinition{BlockParamValue: p, BlkParamVReg: raxVReg}
ctx.vRegMap[p] = raxVReg
ctx.definitions[p] = &backend.SSAValueDefinition{V: p}
ctx.vRegMap[0] = rcxVReg
instr := &ssa.Instruction{}
instr.AsClz(p)
Expand Down Expand Up @@ -434,7 +440,8 @@ L2:
p := b.CurrentBlock().AddParam(b, tc.typ)
m.cpuFeatures = tc.cpuFlags

ctx.definitions[p] = &backend.SSAValueDefinition{BlockParamValue: p, BlkParamVReg: raxVReg}
ctx.vRegMap[p] = raxVReg
ctx.definitions[p] = &backend.SSAValueDefinition{V: p}
ctx.vRegMap[0] = rcxVReg
instr := &ssa.Instruction{}
instr.AsCtz(p)
Expand Down
34 changes: 12 additions & 22 deletions internal/engine/wazevo/backend/isa/amd64/operands.go
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Original file line number Diff line number Diff line change
Expand Up @@ -253,11 +253,11 @@ func (a *amode) String() string {
}

func (m *machine) getOperand_Mem_Reg(def *backend.SSAValueDefinition) (op operand) {
if def.IsFromBlockParam() {
return newOperandReg(def.BlkParamVReg)
if !def.IsFromInstr() {
return newOperandReg(m.c.VRegOf(def.V))
}

if def.SSAValue().Type() == ssa.TypeV128 {
if def.V.Type() == ssa.TypeV128 {
// SIMD instructions require strict memory alignment, so we don't support the memory operand for V128 at the moment.
return m.getOperand_Reg(def)
}
Expand All @@ -273,8 +273,8 @@ func (m *machine) getOperand_Mem_Reg(def *backend.SSAValueDefinition) (op operan
}

func (m *machine) getOperand_Mem_Imm32_Reg(def *backend.SSAValueDefinition) (op operand) {
if def.IsFromBlockParam() {
return newOperandReg(def.BlkParamVReg)
if !def.IsFromInstr() {
return newOperandReg(m.c.VRegOf(def.V))
}

if m.c.MatchInstr(def, ssa.OpcodeLoad) {
Expand All @@ -288,8 +288,8 @@ func (m *machine) getOperand_Mem_Imm32_Reg(def *backend.SSAValueDefinition) (op
}

func (m *machine) getOperand_Imm32_Reg(def *backend.SSAValueDefinition) (op operand) {
if def.IsFromBlockParam() {
return newOperandReg(def.BlkParamVReg)
if !def.IsFromInstr() {
return newOperandReg(m.c.VRegOf(def.V))
}

instr := def.Instr
Expand Down Expand Up @@ -325,22 +325,12 @@ func asImm32(val uint64, allowSignExt bool) (uint32, bool) {

func (m *machine) getOperand_Reg(def *backend.SSAValueDefinition) (op operand) {
var v regalloc.VReg
if def.IsFromBlockParam() {
v = def.BlkParamVReg
if instr := def.Instr; instr != nil && instr.Constant() {
// We inline all the constant instructions so that we could reduce the register usage.
v = m.lowerConstant(instr)
instr.MarkLowered()
} else {
instr := def.Instr
if instr.Constant() {
// We inline all the constant instructions so that we could reduce the register usage.
v = m.lowerConstant(instr)
instr.MarkLowered()
} else {
if n := def.N; n == 0 {
v = m.c.VRegOf(instr.Return())
} else {
_, rs := instr.Returns()
v = m.c.VRegOf(rs[n-1])
}
}
v = m.c.VRegOf(def.V)
}
return newOperandReg(v)
}
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