An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Open Source Architecture Code Analyzer

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)

Advanced Architecture Labs with CVA6

A compiler, assembler, and processor.

Educational computer simulator on a mission to "superscalate" the study of computer architecture fundamentals

An approach to apply concept drifts and ADWIN on the streams event time to reason about the progress of watermarks

Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022

Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC

Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm

EdgeMailer is a tool that tests rate limits of mail providers, it uses libcurl and libuv to make concomitant assynchronous request. This tool is outdated and now is closed source and belongs to YouSendr.

Superscalar OoO RISCV processor written in Chisel

CENOS: The Modern CPU Simulator

Keyed Watermarks in Apache Flink

This repository contains the Labs done in the course COL718 High Performance Computing taught by Prof. Sourav Bansal at IIT, Delhi in Fall 2019

A Flink library to implement both a buffer-based and a speculative out-of-order event arrival handlers for online process discovery

try to design a Single_Emission_Out-of-Order_Pipeline_RISC-V_Processor

2-way Out of Order RISC-V Processor

Go implementation of a bitmap ring-buffer which tracks the state of windowed out-of-order processing over a sequence of logical offsets