This paper was accepted in ASYNC 2018.
Asynchronous circuits are pervasive in modern synchronous systems, but they are still designed and verified in isolation, using dedicated asynchronous design flows, formalisms and tools. We describe a method to verify gate-level asynchronous circuit implementations using formal verification tools and property languages for synchronous logic. We report observations and findings from applying this method to use case designs using an industrial and an open source formal verification tools for synchronous logic, and compare performance and verification capabilities against two verification tools for asynchronous circuits. Finally, we discuss the advantages and practical considerations of bridging synchronous logic verification tools to the domain of asynchronous circuits. Our main conclusion is that, while there are performance penalties, there is still significant value in enabling users to verify asynchronous circuits using tools that may be more familiar, trusted or more widely adopted.
https://tuura.github.io/sync-models-paper/pdfs/paper-final-version.pdf