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This is the v4.4.302-cip69 CIP release
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| include: | ||
| - https://gitlab.com/cip-project/cip-testing/linux-cip-pipelines/raw/master/linux-cip-pipeline.yml | ||
| - https://gitlab.com/cip-project/cip-testing/linux-cip-pipelines/raw/master/trees/linux-4.4.y-cip.yml |
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| # SPDX-License-Identifier: GPL-2.0 | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/arm/renesas,prr.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
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| title: Renesas Product Register | ||
|
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| maintainers: | ||
| - Geert Uytterhoeven <[email protected]> | ||
| - Magnus Damm <[email protected]> | ||
|
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| description: | | ||
| Most Renesas ARM SoCs have a Product Register or Boundary Scan ID | ||
| Register that allows to retrieve SoC product and revision information. | ||
| If present, a device node for this register should be added. | ||
| properties: | ||
| compatible: | ||
| enum: | ||
| - renesas,prr | ||
| - renesas,bsid | ||
| reg: | ||
| maxItems: 1 | ||
|
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| required: | ||
| - compatible | ||
| - reg | ||
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| additionalProperties: false | ||
|
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| examples: | ||
| - | | ||
| prr: chipid@ff000044 { | ||
| compatible = "renesas,prr"; | ||
| reg = <0xff000044 4>; | ||
| }; |
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128 changes: 128 additions & 0 deletions
128
Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
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| TI CPUFreq and OPP bindings | ||
| ================================ | ||
|
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| Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx | ||
| families support different OPPs depending on the silicon variant in use. | ||
| The ti-cpufreq driver can use revision and an efuse value from the SoC to | ||
| provide the OPP framework with supported hardware information. This is | ||
| used to determine which OPPs from the operating-points-v2 table get enabled | ||
| when it is parsed by the OPP framework. | ||
|
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| Required properties: | ||
| -------------------- | ||
| In 'cpus' nodes: | ||
| - operating-points-v2: Phandle to the operating-points-v2 table to use. | ||
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| In 'operating-points-v2' table: | ||
| - compatible: Should be | ||
| - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx SoCs | ||
| - syscon: A phandle pointing to a syscon node representing the control module | ||
| register space of the SoC. | ||
|
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| Optional properties: | ||
| -------------------- | ||
| For each opp entry in 'operating-points-v2' table: | ||
| - opp-supported-hw: Two bitfields indicating: | ||
| 1. Which revision of the SoC the OPP is supported by | ||
| 2. Which eFuse bits indicate this OPP is available | ||
|
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| A bitwise AND is performed against these values and if any bit | ||
| matches, the OPP gets enabled. | ||
|
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| Example: | ||
| -------- | ||
|
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| /* From arch/arm/boot/dts/am33xx.dtsi */ | ||
| cpus { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| cpu@0 { | ||
| compatible = "arm,cortex-a8"; | ||
| device_type = "cpu"; | ||
| reg = <0>; | ||
|
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| operating-points-v2 = <&cpu0_opp_table>; | ||
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| clocks = <&dpll_mpu_ck>; | ||
| clock-names = "cpu"; | ||
|
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| clock-latency = <300000>; /* From omap-cpufreq driver */ | ||
| }; | ||
| }; | ||
|
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| /* | ||
| * cpu0 has different OPPs depending on SoC revision and some on revisions | ||
| * 0x2 and 0x4 have eFuse bits that indicate if they are available or not | ||
| */ | ||
| cpu0_opp_table: opp-table { | ||
| compatible = "operating-points-v2-ti-cpu"; | ||
| syscon = <&scm_conf>; | ||
|
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| /* | ||
| * The three following nodes are marked with opp-suspend | ||
| * because they can not be enabled simultaneously on a | ||
| * single SoC. | ||
| */ | ||
| opp50@300000000 { | ||
| opp-hz = /bits/ 64 <300000000>; | ||
| opp-microvolt = <950000 931000 969000>; | ||
| opp-supported-hw = <0x06 0x0010>; | ||
| opp-suspend; | ||
| }; | ||
|
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| opp100@275000000 { | ||
| opp-hz = /bits/ 64 <275000000>; | ||
| opp-microvolt = <1100000 1078000 1122000>; | ||
| opp-supported-hw = <0x01 0x00FF>; | ||
| opp-suspend; | ||
| }; | ||
|
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| opp100@300000000 { | ||
| opp-hz = /bits/ 64 <300000000>; | ||
| opp-microvolt = <1100000 1078000 1122000>; | ||
| opp-supported-hw = <0x06 0x0020>; | ||
| opp-suspend; | ||
| }; | ||
|
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| opp100@500000000 { | ||
| opp-hz = /bits/ 64 <500000000>; | ||
| opp-microvolt = <1100000 1078000 1122000>; | ||
| opp-supported-hw = <0x01 0xFFFF>; | ||
| }; | ||
|
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| opp100@600000000 { | ||
| opp-hz = /bits/ 64 <600000000>; | ||
| opp-microvolt = <1100000 1078000 1122000>; | ||
| opp-supported-hw = <0x06 0x0040>; | ||
| }; | ||
|
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| opp120@600000000 { | ||
| opp-hz = /bits/ 64 <600000000>; | ||
| opp-microvolt = <1200000 1176000 1224000>; | ||
| opp-supported-hw = <0x01 0xFFFF>; | ||
| }; | ||
|
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| opp120@720000000 { | ||
| opp-hz = /bits/ 64 <720000000>; | ||
| opp-microvolt = <1200000 1176000 1224000>; | ||
| opp-supported-hw = <0x06 0x0080>; | ||
| }; | ||
|
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| oppturbo@720000000 { | ||
| opp-hz = /bits/ 64 <720000000>; | ||
| opp-microvolt = <1260000 1234800 1285200>; | ||
| opp-supported-hw = <0x01 0xFFFF>; | ||
| }; | ||
|
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| oppturbo@800000000 { | ||
| opp-hz = /bits/ 64 <800000000>; | ||
| opp-microvolt = <1260000 1234800 1285200>; | ||
| opp-supported-hw = <0x06 0x0100>; | ||
| }; | ||
|
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| oppnitro@1000000000 { | ||
| opp-hz = /bits/ 64 <1000000000>; | ||
| opp-microvolt = <1325000 1298500 1351500>; | ||
| opp-supported-hw = <0x04 0x0200>; | ||
| }; | ||
| }; |
9 changes: 9 additions & 0 deletions
9
Documentation/devicetree/bindings/display/panel/edt,etm043080dh6gp.txt
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| Emerging Display Technology Corp. ETM043080DH6-GP 4.3" WQVGA TFT LCD panel | ||
|
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| Required properties: | ||
| - compatible: should be "edt,etm043080dh6gp" | ||
|
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| ETM043080DH6-GP is 480x272 TFT Display with capacitive touchscreen. | ||
|
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| This binding is compatible with the simple-panel binding, which is specified | ||
| in simple-panel.txt in this directory. |
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