Team and Publication Changes (#89)

* Updated team and alumni pages * Added alumni to team page, added css for square images, updated team members * Corrected typos * LinkedIn profiles updated * Revert "Changes related to news (#79)" This reverts commit d161fba. * Revert "Revert "Changes related to news (#79)"" This reverts commit 800aa71. * Merge changes, conflicts resolved * Updated co-guides * Updated co-guides * Updated co-guides * Image deleted * Publications updated;Team Members updated * Duplicate removed --------- Co-authored-by: Soumya Banerjee <[email protected]>
utpalbora · Jan 24, 2024 · c0c36aa · c0c36aa
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diff --git a/_data/alumni.yml b/_data/alumni.yml
@@ -1,11 +1,3 @@
-- name: Utpal Bora
-  type: alum
-  value: phd
-  info: M.Tech + PhD, 2014-2022
-  photo: utpal.jpg
-  next : PostDoc at University of Cambridge, UK
-  thesis : Techniques for Static Detection of Data-Races in OpenMP Programs
-
 - name: Shalini Jain
   type: alum
   value: phd
@@ -14,6 +6,14 @@
   next : Qualcomm compilers team
   thesis : Reinforcement Learning based Compiler Optimizations for Size and Performance
 
+- name: Utpal Bora
+  type: alum
+  value: phd
+  info: M.Tech + PhD, 2014-2022
+  photo: utpal.jpg
+  next : PostDoc at University of Cambridge, UK
+  thesis : Techniques for Static Detection of Data-Races in OpenMP Programs
+
 - name: Kuldeep Gautam
   type: alum
   value: mtech

diff --git a/_data/publist.yml b/_data/publist.yml
@@ -1,7 +1,29 @@
+- shortname: "ml-compiler-bridge"
+  title: "The Next 700 ML-Enabled Compiler Optimizations"    
+  short_title: "ML-Compiler-Bridge"
+  authors: "S. VenkataKeerthy, Siddharth Jain, Umesh Kalvakuntla, Pranav Sai Gorantla, Rajiv Shailesh Chitale, Eugene Brevdo, Albert Cohen, Mircea Trofin, Ramakrishna Upadrasta"
+  description: ""
+  domain: "ML4Compilers"
+  subdomain: "IR2Vec"
+  year: "2024"
+  publishedAt: "CC"
+  project: 0
+  publication: 1
+  type: "Conference"
+  # image: ""   
+  highlight: 1
+  github_link: ""
+  citation: ""
+  paper_link: ""
+  poster_link: ""
+  slides_link: ""
+  videos_link: ""
+  arxiv_link: "https://arxiv.org/abs/2311.10800"
+
 - shortname: "ml-llvm-tools"
   title: "ML-LLVM-Tools: Towards Seamless Integration of Machine Learning in Compiler Optimizations"    
   short_title: "ML-LLVM-Tools"
-  authors: "Siddharth Jain, S. VenkataKeerthy, Umesh Kalvakuntla, Albert Cohen, Ramakrishna Upadrast"
+  authors: "Siddharth Jain, S. VenkataKeerthy, Umesh Kalvakuntla, Albert Cohen, Ramakrishna Upadrasta"
   description: ""
   domain: "ML4Compilers"
   subdomain: "IR2Vec"
@@ -16,8 +38,8 @@
   citation: ""
   paper_link: ""
   poster_link: ""
-  slides_link: ""
-  videos_link: ""
+  slides_link: "https://llvm.org/devmtg/2023-05/slides/TechnicalTalks-May10/10-Venkat-ML-LLVM-Tools.pdf"
+  videos_link: "https://www.youtube.com/watch?v=3RYPv27Tp6s"
   arxiv_link: ""
 
 
@@ -100,7 +122,7 @@
   highlight: 1
   github_link: ""   
   citation: "" 
-  paper_link: "" 
+  paper_link: "https://ieeexplore.ieee.org/document/10026979" 
   poster_link: "" 
   slides_link: ""  
   videos_link: "" 
@@ -369,27 +391,7 @@
   # image: "" 
   highlight: 1
   github_link: ""
-  citation: "TY  - JOUR
-  AU  - Jain, Shalini
-  AU  - Bora, Utpal
-  AU  - Kumar, Prateek
-  AU  - Sinha, Vaibhav B.
-  AU  - Purini, Suresh
-  AU  - Upadrasta, Ramakrishna
-  PY  - 2019
-  DA  - 2019/06/01
-  TI  - An analysis of executable size reduction by LLVM passes
-  JO  - CSI Transactions on ICT
-  SP  - 105
-  EP  - 110
-  VL  - 7
-  IS  - 2
-  AB  - The formidable increase in the number of smaller and smarter embedded devices has compelled programmers to develop more and more specialized application programs for these systems. These resource intensive programs that have to be executed on limited memory systems make a strong case for compiler optimizations that reduce the executable size of programs. Standard compilers (like LLVM) offer an out-of-the-box -Oz optimization option—just a series of compiler optimization passes—that is specifically targeted for the reduction of the generated executable size. In this paper, we aim to analyze the effects of optimizations of LLVM compiler on the reduction of executable size. Specifically, we take the size of the executable as a metric and attempt to divide the -Oz series into logical groups and study their individual effects; while also study the effect of their combinations. Our preliminary study over SPEC CPU 2017 benchmarks gives us an insight into the comparative effect of the groups of passes on the executable size. Our work has potential to enable the user to tailor a custom series of passes so as to obtain the desired executable size.
-  SN  - 2277-9086
-  UR  - https://doi.org/10.1007/s40012-019-00248-5
-  DO  - 10.1007/s40012-019-00248-5
-  ID  - Jain2019
-  ER  - "
+  citation: ""
   paper_link: "https://link.springer.com/article/10.1007/s40012-019-00248-5"
   poster_link: ""
   slides_link: ""
@@ -412,15 +414,7 @@
   # image: ""   
   highlight: 1
   github_link: "https://github.com/abhishek111226/Texturizing-PPCG"
-  citation: "@INPROCEEDINGS{9188095,
-  author={Patwardhan, Abhishek A. and Upadrasta, Ramakrishna},
-  booktitle={2019 International Conference on High Performance Computing & Simulation (HPCS)}, 
-  title={Polyhedral Model Guided Automatic GPU Cache Exploitation Framework}, 
-  year={2019},
-  volume={},
-  number={},
-  pages={496-503},
-  doi={10.1109/HPCS48598.2019.9188095}}"
+  citation: ""
   paper_link: "https://ieeexplore.ieee.org/document/9188095"
   poster_link: ""
   slides_link: ""
@@ -453,24 +447,24 @@
 
 
 
-- shortname: ""
-  title: "Exploiting GPU caches By Polyhedral Compilation" 
-  authors: "Abhishek A Patwardhan & Ramakrishna Upadrasta"
-  description: ""
-  year: "2019"
-  publishedAt: "OMASE"
-  project: 0
-  publication: 0
-  type: "Talks"
-  # image: ""  
-  highlight: 1
-  github_link: ""
-  citation: ""
-  paper_link: ""
-  poster_link: ""
-  slides_link: ""
-  videos_link: ""
-  arxiv_link: ""
+# - shortname: ""
+#   title: "Exploiting GPU caches By Polyhedral Compilation" 
+#   authors: "Abhishek A Patwardhan & Ramakrishna Upadrasta"
+#   description: ""
+#   year: "2019"
+#   publishedAt: "OMASE"
+#   project: 0
+#   publication: 0
+#   type: "Talks"
+#   # image: ""  
+#   highlight: 1
+#   github_link: ""
+#   citation: ""
+#   paper_link: ""
+#   poster_link: ""
+#   slides_link: ""
+#   videos_link: ""
+#   arxiv_link: ""
 
 
 

diff --git a/_data/team_members.yml b/_data/team_members.yml
@@ -161,7 +161,7 @@
     link: https://www.linkedin.com/in/raj-ambekar-b090a474/
   photo: Raj_Ambekar.png
   info: M.Tech RA, started August 2022 (co-advised by Dr. Jyothi Vedurada)
-  email: cs23mtech12006 [AT] iith [DOT] ac [DOT] in
+  email: cs22mtech12008 [AT] iith [DOT] ac [DOT] in
   interests: Compiler Optimization, Code Compliance
 
 - name: Neha Bhargava
@@ -171,18 +171,18 @@
     link: https://in.linkedin.com/in/neha-bhargava-0b8a69164
   photo: neha.jpg
   info: M.Tech RA, started July 2023 (co-advised by Dr. Rajesh Kedia)
-  email: cs22mtech12011 [AT] iith [DOT] ac [DOT] in
-  interests: Compilers, Computer Architecture
+  email: cs23mtech12006 [AT] iith [DOT] ac [DOT] in
+  interests: Compilers, Computer Architecture, Hardware Security
 
-- name: Joshi Jay Prafulkumar
-  type: mtech
-  url :
-    value: 1
-    link: https://github.com/Jay-Joshi-GIT
-  photo: jay.jpg
-  info: M.Tech RA, started July 2023
-  email: cs22mtech12004 [AT] iith [DOT] ac [DOT] in
-  interests: Compiler Optimization, Embedded Systems
+# - name: Joshi Jay Prafulkumar
+#   type: mtech
+#   url :
+#     value: 1
+#     link: https://github.com/Jay-Joshi-GIT
+#   photo: jay.jpg
+#   info: M.Tech RA, started July 2023
+#   email: cs22mtech12004 [AT] iith [DOT] ac [DOT] in
+#   interests: Compiler Optimization, Embedded Systems
 
 - name: Siddhartha Neyagapula
   type: mtech
@@ -191,9 +191,19 @@
     link: https://github.com/siddu12
   photo: siddhartha.jpg
   info: M.Tech RA, started July 2023 (co-advised by Dr. Jyothi Vedurada)
-  email: cs22mtech12010 [AT] iith [DOT] ac [DOT] in
+  email: cs23mtech12010 [AT] iith [DOT] ac [DOT] in
   interests: Compiler Optimization, Code Compliance
 
+- name: Aayush Shrivastava
+  type: mtech
+  url :
+    value: 1
+    link: https://www.linkedin.com/in/iamaayushrivastava/
+  photo: aayush.jpg
+  info: M.Tech RA, started Jan 2024
+  email: cs24mtech02001 [AT] iith [DOT] ac [DOT] in
+  interests: Machine Learning, Compiler Optimizations
+
 # - name: Raghvendra Gupta 
 #   type: mtech
 #   url :

diff --git a/_pages/ml_compiler_bridge.md b/_pages/ml_compiler_bridge.md
@@ -0,0 +1,25 @@
+---
+title: "The Next 700 ML-Enabled Compiler Optimizations"
+redirect_from:
+    - /research/ml-compiler-bridge
+layout: textlay
+excerpt: "IITH Compilers Team -- Research"
+sitemap: false
+permalink: /publications/ml-compiler-bridge/
+---
+
+# The Next 700 ML-Enabled Compiler Optimizations
+*S. VenkataKeerthy, Siddharth Jain, Umesh Kalvakuntla, Pranav Sai Gorantla, Rajiv Shailesh Chitale, Eugene Brevdo, Albert Cohen, Mircea Trofin, Ramakrishna Upadrasta*
+### Abstract
+
+There is a growing interest in enhancing compiler optimizations with ML models, yet interactions between compilers
+and ML frameworks remain challenging. Some optimizations require tightly coupled models and compiler internals,
+raising issues with modularity, performance and framework
+independence. Practical deployment and transparency for
+the end-user are also important concerns. We propose MLCompiler-Bridge to enable ML model development within
+a traditional Python framework while making end-to-end integration with an optimizing compiler possible and efficient.
+We evaluate it on both research and production use cases, for
+training and inference, over several optimization problems,
+multiple compilers and its versions, and gym infrastructures.
+
+
diff --git a/images/teampic/aayush.jpg b/images/teampic/aayush.jpg
diff --git a/images/teampic/jay.jpg b/images/teampic/jay.jpg