Add hierarchical identifier check

veryl-lang · Aug 1, 2023 · 4dc5ba6 · 4dc5ba6
1 parent dddd628
commit 4dc5ba6
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Showing 3 changed files with 12 additions and 15 deletions.
diff --git a/crates/analyzer/src/handlers/create_reference.rs b/crates/analyzer/src/handlers/create_reference.rs
@@ -40,19 +40,18 @@ impl<'a> VerylGrammarTrait for CreateReference<'a> {
                         }
                     } else {
                         let is_single_identifier = SymbolPath::from(arg).as_slice().len() == 1;
-                        if is_single_identifier {
-                            let name = arg.identifier.identifier_token.text();
-                            if name != "_" {
-                                self.errors.push(AnalyzerError::undefined_identifier(
-                                    &name,
-                                    self.text,
-                                    &arg.identifier.identifier_token,
-                                ));
-                            }
+                        let name = arg.identifier.identifier_token.text();
+                        if name != "_" || !is_single_identifier {
+                            self.errors.push(AnalyzerError::undefined_identifier(
+                                &name,
+                                self.text,
+                                &arg.identifier.identifier_token,
+                            ));
                         }
                     }
                 }
                 Err(err) => {
+                    // TODO check SV-side member to suppress error
                     let name = format!("{}", err.last_found.token.text);
                     let member = format!("{}", err.not_found);
                     self.errors.push(AnalyzerError::unknown_member(

diff --git a/testcases/sv/11_let.sv b/testcases/sv/11_let.sv
@@ -9,7 +9,6 @@ module veryl_testcase_Module11;
     assign _c = 1;
 
     // assign declaration
-    assign b    = 1;
-    assign bb   = 1;
-    assign aa.a = 1;
+    assign b  = 1;
+    assign bb = 1;
 endmodule
diff --git a/testcases/vl/11_let.vl b/testcases/vl/11_let.vl
@@ -8,7 +8,6 @@ module Module11 {
     var _c: logic<10> = 1;
 
     // assign declaration
-    assign b    = 1;
-    assign bb   = 1;
-    assign aa.a = 1;
+    assign b  = 1;
+    assign bb = 1;
 }