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Ruige Lee edited this page Jan 22, 2021 · 2 revisions

instruction fetch

In this version, this stage will align the address to 64bits and generate an AXI transmission，But the address will transfer to the next stage with no modify.

In the following version, and icache will be implemented here.

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pc generate

instruction fetch

instruction queue

instruction decode

instruction FIFO

dispatch

issue

execute

writeback

commit

out of order implementation

Parity memory

inner bus

FPGA Implementation

Basic Element

D Flip-Flop

D Flip-Flop with enable

RS Flip-Flop

Sync FIFO

Bypass FIFO

Ring Stack

SRAM

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