Dear all,
We are happy to announce the binary release of our MSFSMs Tool.
The goal of the MSFSMs tool is to perform Petri Net to Verilog Logic Synthesis, by decomposing the provided Petri Net
specification first into Strongly-Connected S-nets and then into Multiple, Synchronised FSMs (MSFSMs), which may be
exported in Verilog format. One key benefit of this flow, over state-based methods, e.g. State Graph based analysis
and Synthesis, is that it is of polynomial complexity.
The Verilog output is comprised of multiple FSM specifications (synthesisable), and a Top-Level wrapper.
The exported Verilog FSMs may be implemented as (i) one-hot asynchronous FSMs, (ii) as synchronous FSMs, or (iii) using
an arbitrary async/sync encoding. The latter is NOT yet supported.
The MSFSMs Tool supports all Petri Net classes, including Asymetric Choice(AC) and General Petri Net, provided that the
specification is well-formed (live and 1-bounded).
The tool is TCL based, and sample scripts and benchmarks are provided. Please take a look at the documentation.
We are very keen on working with interested collaborators on asynchronous synthesis of Petri Nets, particularly on
tackling the FSM encoding, co-encoding problem, as well as state minimisation, for the (MS)FSMs extracted from the
original Petri Net. We will be happy to provide support for anyone who is willing to try out our flow and work with
our tool.
Please feel free to contact us for further information or support.