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Updates for changes from attributes to properties for MLIR v17 #7

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2 changes: 1 addition & 1 deletion psy/apply_stencil.py
Original file line number Diff line number Diff line change
Expand Up @@ -334,7 +334,7 @@ def get_dag_top_level(node):
def handle_stencil_for_target(self, visitor, index, target_var_name, for_loop: psy_ir.Loop, rewriter: PatternRewriter, unique_var_idx:int):
read_vars=[]
access_variables=[]
for read_var_name in visitor.written_to_read[index]:
for read_var_name in sorted(visitor.written_to_read[index]):
read_var_v=visitor.read_variables[read_var_name]
read_vars.append(read_var_v.var)

Expand Down
11 changes: 7 additions & 4 deletions psy/extract_stencil.py
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ def wrap_stencil_in_func(name, input_types, operations):
input_types_translated=[]
for typ in input_types:
if isinstance(typ, fir.LLVMPointerType):
input_types_translated.append(llvm.LLVMPointerType.typed(typ.type))
input_types_translated.append(llvm.LLVMPointerType.opaque()) #typed(typ.type))
else:
input_types_translated.append(typ)

Expand Down Expand Up @@ -134,6 +134,8 @@ def match_and_rewrite(self, apply_stencil_op: stencil.ApplyOp, rewriter: Pattern
assert parent_func is not None and isinstance(parent_func, func.FuncOp)
if "_InternalBridgeStencil_" in parent_func.sym_name.data: return


# TODO (MJ): We need to ensure these arguments are ordered (sorted) consistently for the FPGA host code (match HLS kernel)
input_args_to_ops={}
stencil_ops=[]
for input_arg in apply_stencil_op.args:
Expand Down Expand Up @@ -166,6 +168,7 @@ def match_and_rewrite(self, apply_stencil_op: stencil.ApplyOp, rewriter: Pattern
arg_ops=[]
op_types=[]
ops_to_add=[]

for key, value in itertools.chain(input_args_to_ops.items(), output_args_to_ops.items()):
external_load_op=ExtractStencilOps.find_ExternalLoad(value)
if external_load_op is not None:
Expand All @@ -192,7 +195,7 @@ def match_and_rewrite(self, apply_stencil_op: stencil.ApplyOp, rewriter: Pattern
function_name="_InternalBridgeStencil_"+str(self.bridge_id)
self.bridge_id+=1

call_stencil=fir.Call.create(attributes={"callee": builtin.SymbolRefAttr(function_name)}, operands=[el.results[0] for el in arg_ops], result_types=[])
call_stencil=fir.Call.create(properties={"callee": builtin.SymbolRefAttr(function_name)}, operands=[el.results[0] for el in arg_ops], result_types=[])
parent.insert_ops_before(ops_to_add+[call_stencil], apply_stencil_op)

for op in stencil_ops:
Expand Down Expand Up @@ -320,7 +323,7 @@ def match_and_rewrite(self, op: stencil.ExternalLoadOp, rewriter: PatternRewrite
# be an LLVM pointer to this
if not isinstance(ptr_type, llvm.LLVMPointerType):
nt=ConnectExternalLoadToFunctionInput.get_nested_type(ptr_type, fir.SequenceType)
ptr_type=llvm.LLVMPointerType.typed(nt.type)
ptr_type=llvm.LLVMPointerType.opaque() #typed(nt.type)

array_typ=llvm.LLVMArrayType.from_size_and_type(builtin.IntAttr(number_dims), builtin.i64)
struct_type=llvm.LLVMStructType.from_type_list([ptr_type, ptr_type, builtin.i64, array_typ, array_typ])
Expand Down Expand Up @@ -354,7 +357,7 @@ def match_and_rewrite(self, op: stencil.ExternalLoadOp, rewriter: PatternRewrite

#if isinstance(ptr_type, llvm.LLVMPointerType):
shape_int = [i if isinstance(i, int) else i.value.data for i in ConnectExternalLoadToFunctionInput.get_c_style_array_shape(array_type)]
target_memref_type=MemRefType(ptr_type.type, shape_int)
target_memref_type=MemRefType(nt.type, shape_int)

unrealised_conv_cast_op=builtin.UnrealizedConversionCastOp.create(operands=[insert_stride_op.results[0]], result_types=[target_memref_type])
ops_to_add.append(unrealised_conv_cast_op)
Expand Down
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