Add support for auto naming of JLC PCB fabrication

yaqwsx · Jan 26, 2025 · f418066 · f418066
1 parent 8c980f3
commit f418066
Show file tree

Hide file tree

Showing 3 changed files with 10 additions and 3 deletions.
diff --git a/docs/fabrication/jlcpcb.md b/docs/fabrication/jlcpcb.md
@@ -7,7 +7,8 @@ kikit fab jlcpcb [OPTIONS] BOARD OUTPUTDIR
 
 When you run this command, you will find file `gerbers.zip` in `OUTPUTDIR`. This
 file can be directly uploaded to JLC PCB site. KiKit automatically detects the
-number of layers.
+number of layers. If you would like to include the project name in the archive
+name, you can supply `--autoname`
 
 If you want to name your files differently, you can specify `--nametemplate`.
 This option takes a string that should contain `{}`. This string will be

diff --git a/kikit/fab/jlcpcb.py b/kikit/fab/jlcpcb.py
@@ -56,7 +56,8 @@ def bomToCsv(bomData, filename):
                 writer.writerow([value, ",".join(refChunk), footprint, lcsc])
 
 def exportJlcpcb(board, outputdir, assembly, schematic, ignore, field,
-           corrections, correctionpatterns, missingerror, nametemplate, drc):
+           corrections, correctionpatterns, missingerror, nametemplate, drc,
+           autoname):
     """
     Prepare fabrication files for JLCPCB including their assembly service
     """
@@ -74,7 +75,11 @@ def exportJlcpcb(board, outputdir, assembly, schematic, ignore, field,
     shutil.rmtree(gerberdir, ignore_errors=True)
     gerberImpl(board, gerberdir)
 
-    archiveName = expandNameTemplate(nametemplate, "gerbers", loadedBoard)
+    if autoname:
+        boardName = os.path.basename(board.replace(".kicad_pcb", ""))
+        archiveName = expandNameTemplate(nametemplate, boardName + "-gerbers", loadedBoard)
+    else:
+        archiveName = expandNameTemplate(nametemplate, "gerbers", loadedBoard)
     shutil.make_archive(os.path.join(outputdir, archiveName), "zip", outputdir, "gerber")
 
     if not assembly:

diff --git a/kikit/fab_ui.py b/kikit/fab_ui.py
@@ -31,6 +31,7 @@ def fabCommand(f):
     help="Comma separated list of component fields with the correction value. First existing field is used")
 @click.option("--correctionpatterns", type=click.Path(dir_okay=False))
 @click.option("--missingError/--missingWarn", help="If a non-ignored component misses LCSC field, fail")
+@click.option("--autoname", is_flag=True, help="Automatically name the output files based on the board name")
 def jlcpcb(**kwargs):
     """
     Prepare fabrication files for JLCPCB including their assembly service