README.md

RTL Cheat

VHDL and Verilog minimal examples. IC design and synthesis tutorials. Asserts used wherever possible.

1. Getting started
2. Examples
   1. VHDL
   2. Verilog
   3. Interactive
3. Theory
   1. Introduction
      1. Motivation
   2. Synthesis
      1. Standard cell library
      2. Yosys
   3. History
   4. Standards
   5. Wave files
      1. VCD
      2. GTKWave
   6. Language
   7. Behavioural vs structural
   8. Design
      1. Clock tree
      2. CPU
         1. Y86
   9. Latch
   10. Vendors
       1. Synopsys
          1. VCS
       2. Cadence
          1. Incisive
          2. SimVision
          3. Genus
   11. FPGA
   12. Microchip fabrication
   13. Memory model
4. Simulators
   1. GHDL
5. Glossary
6. Bibliography