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s32: soc: s32k148: add support for ENET
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Add support for ENET.

Implement workarounds for known ENET CRC issues on S32K148 in fsl_enet driver.

Signed-off-by: Kevin Shaju <[email protected]>
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@KevShaju @marcin-wierzbicki
KevShaju authored and marcin-wierzbicki committed Feb 11, 2025
1 parent c714658 commit 3e9922d
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Showing 5 changed files with 150 additions and 101 deletions.
17 changes: 14 additions & 3 deletions mcux/mcux-sdk/drivers/enet/fsl_enet.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1627,10 +1627,21 @@ status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length, uint8_t ri
{
isReturn = true;
/* The last buffer descriptor in the frame check the status of the received frame. */
if (0U != (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_ERR_MASK))
if (IS_ENABLED(CONFIG_ETH_NXP_ENET_IGNORE_RX_CRC_PHY_ERROR))
{
result = kStatus_ENET_RxFrameError;
break;
if (0U != (curBuffDescrip->control & NO_CRC_ENET_BUFFDESCRIPTOR_RX_ERR_MASK))
{
result = kStatus_ENET_RxFrameError;
break;
}
}
else
{
if (0U != (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_ERR_MASK))
{
result = kStatus_ENET_RxFrameError;
break;
}
}
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
if (0U != (curBuffDescrip->controlExtend1 & ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK))
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3 changes: 3 additions & 0 deletions mcux/mcux-sdk/drivers/enet/fsl_enet.h
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Original file line number Diff line number Diff line change
Expand Up @@ -112,6 +112,9 @@
#define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \
(ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \
ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK)
#define NO_CRC_ENET_BUFFDESCRIPTOR_RX_ERR_MASK \
(ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \
ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK)
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \
(ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK)
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12 changes: 11 additions & 1 deletion s32/drivers/s32k1/BaseNXP/header/S32K148_ENET.h
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Original file line number Diff line number Diff line change
Expand Up @@ -201,7 +201,7 @@ typedef struct {
/** Array initializer of ENET peripheral base addresses */
#define IP_ENET_BASE_ADDRS { IP_ENET_BASE }
/** Array initializer of ENET peripheral base pointers */
#define IP_ENET_BASE_PTRS { IP_ENET }
#define ENET_BASE_PTRS { IP_ENET }

/* ----------------------------------------------------------------------------
-- ENET Register Masks
Expand Down Expand Up @@ -1498,6 +1498,16 @@ typedef struct {
* @}
*/ /* end of group ENET_Register_Masks */

/* ENET Buffer Descriptor and Buffer Address Alignment. */
#define ENET_BUFF_ALIGNMENT (64U)

/* Interrupt vectors for the ENET peripheral type */
#define ENET_Transmit_IRQS { ENET_TX_Buffer_IRQn }
#define ENET_Receive_IRQS { ENET_RX_Buffer_IRQn }
#define ENET_Error_IRQS { ENET_PRE_IRQn }
#define ENET_1588_Timer_IRQS { ENET_Timer_IRQn }
#define ENET_Ts_IRQS { ENET_Timer_IRQn }

/*!
* @}
*/ /* end of group ENET_Peripheral_Access_Layer */
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75 changes: 38 additions & 37 deletions s32/soc/s32k148/include/Clock_Ip_Cfg_Defines.h
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Original file line number Diff line number Diff line change
Expand Up @@ -74,12 +74,12 @@ extern "C"{
/**
* @brief Max number of selectors
*/
#define CLOCK_IP_SELECTORS_COUNT (32U)
#define CLOCK_IP_SELECTORS_COUNT (33U)

/**
* @brief Max number of dividers
*/
#define CLOCK_IP_DIVIDERS_COUNT (20U)
#define CLOCK_IP_DIVIDERS_COUNT (21U)

/**
* @brief Max number of divider triggers
Expand All @@ -104,7 +104,7 @@ extern "C"{
/**
* @brief Max number of clock gates
*/
#define CLOCK_IP_GATES_COUNT (43U)
#define CLOCK_IP_GATES_COUNT (44U)

/**
* @brief Max number of clock monitoring units
Expand Down Expand Up @@ -233,40 +233,41 @@ extern "C"{
#define CLOCK_IP_HAS_DMA0_CLK 55U
#define CLOCK_IP_HAS_DMAMUX0_CLK 56U
#define CLOCK_IP_HAS_EIM0_CLK 57U
#define CLOCK_IP_HAS_ERM0_CLK 58U
#define CLOCK_IP_HAS_EWM0_CLK 59U
#define CLOCK_IP_HAS_FLEXCAN0_CLK 60U
#define CLOCK_IP_HAS_FLEXCAN1_CLK 61U
#define CLOCK_IP_HAS_FLEXCAN2_CLK 62U
#define CLOCK_IP_HAS_FlexIO_CLK 63U
#define CLOCK_IP_HAS_FTFC_CLK 64U
#define CLOCK_IP_HAS_FTM0_CLK 65U
#define CLOCK_IP_HAS_FTM1_CLK 66U
#define CLOCK_IP_HAS_FTM2_CLK 67U
#define CLOCK_IP_HAS_FTM3_CLK 68U
#define CLOCK_IP_HAS_FTM4_CLK 69U
#define CLOCK_IP_HAS_FTM5_CLK 70U
#define CLOCK_IP_HAS_LPI2C0_CLK 71U
#define CLOCK_IP_HAS_LPIT0_CLK 72U
#define CLOCK_IP_HAS_LPSPI0_CLK 73U
#define CLOCK_IP_HAS_LPSPI1_CLK 74U
#define CLOCK_IP_HAS_LPSPI2_CLK 75U
#define CLOCK_IP_HAS_LPTMR0_CLK 76U
#define CLOCK_IP_HAS_LPUART0_CLK 77U
#define CLOCK_IP_HAS_LPUART1_CLK 78U
#define CLOCK_IP_HAS_LPUART2_CLK 79U
#define CLOCK_IP_HAS_MPU0_CLK 80U
#define CLOCK_IP_HAS_MSCM0_CLK 81U
#define CLOCK_IP_HAS_PDB0_CLK 82U
#define CLOCK_IP_HAS_PDB1_CLK 83U
#define CLOCK_IP_HAS_PORTA_CLK 84U
#define CLOCK_IP_HAS_PORTB_CLK 85U
#define CLOCK_IP_HAS_PORTC_CLK 86U
#define CLOCK_IP_HAS_PORTD_CLK 87U
#define CLOCK_IP_HAS_PORTE_CLK 88U
#define CLOCK_IP_HAS_RTC0_CLK 89U
#define CLOCK_IP_HAS_TRACE_CLK 90U
#define CLOCK_IP_FEATURE_NAMES_NO 91U
#define CLOCK_IP_HAS_ENET_CLK 58U
#define CLOCK_IP_HAS_ERM0_CLK 59U
#define CLOCK_IP_HAS_EWM0_CLK 60U
#define CLOCK_IP_HAS_FLEXCAN0_CLK 61U
#define CLOCK_IP_HAS_FLEXCAN1_CLK 62U
#define CLOCK_IP_HAS_FLEXCAN2_CLK 63U
#define CLOCK_IP_HAS_FlexIO_CLK 64U
#define CLOCK_IP_HAS_FTFC_CLK 65U
#define CLOCK_IP_HAS_FTM0_CLK 66U
#define CLOCK_IP_HAS_FTM1_CLK 67U
#define CLOCK_IP_HAS_FTM2_CLK 68U
#define CLOCK_IP_HAS_FTM3_CLK 69U
#define CLOCK_IP_HAS_FTM4_CLK 70U
#define CLOCK_IP_HAS_FTM5_CLK 71U
#define CLOCK_IP_HAS_LPI2C0_CLK 72U
#define CLOCK_IP_HAS_LPIT0_CLK 73U
#define CLOCK_IP_HAS_LPSPI0_CLK 74U
#define CLOCK_IP_HAS_LPSPI1_CLK 75U
#define CLOCK_IP_HAS_LPSPI2_CLK 76U
#define CLOCK_IP_HAS_LPTMR0_CLK 77U
#define CLOCK_IP_HAS_LPUART0_CLK 78U
#define CLOCK_IP_HAS_LPUART1_CLK 79U
#define CLOCK_IP_HAS_LPUART2_CLK 80U
#define CLOCK_IP_HAS_MPU0_CLK 81U
#define CLOCK_IP_HAS_MSCM0_CLK 82U
#define CLOCK_IP_HAS_PDB0_CLK 83U
#define CLOCK_IP_HAS_PDB1_CLK 84U
#define CLOCK_IP_HAS_PORTA_CLK 85U
#define CLOCK_IP_HAS_PORTB_CLK 86U
#define CLOCK_IP_HAS_PORTC_CLK 87U
#define CLOCK_IP_HAS_PORTD_CLK 88U
#define CLOCK_IP_HAS_PORTE_CLK 89U
#define CLOCK_IP_HAS_RTC0_CLK 90U
#define CLOCK_IP_HAS_TRACE_CLK 91U
#define CLOCK_IP_FEATURE_NAMES_NO 92U

/*==================================================================================================
ENUMS
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