arch: Added initial OpenRISC port #83933

jhol · 2025-01-14T00:30:22Z

This patch adds support for the OpenRISC 1000 (or1k) architecture: a MIPS-like open hardware ISA which was first introduced in 2000.

This patch adds basic architecture support for the architecture, as well as a board and soc support for the Qemu virtual ork1ksim board.

github-actions · 2025-01-14T00:31:07Z

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jhol · 2025-01-14T00:32:45Z

@stffrdhrn Please feel free to comment. This work was the origin of the TTMR fix for Qemu.

jhol · 2025-01-14T01:43:21Z

The tests will not be able to complete because the tool-chain does not have the or1k-elf compiler or Qemu 9.2.0.

nashif · 2025-01-16T17:36:01Z

@jhol please split into multiple commits, see https://docs.zephyrproject.org/latest/contribute/contributor_expectations.html#multiple-commits-on-a-single-pr for reference.

jhol · 2025-01-16T22:52:42Z

please split into multiple commits

This has now been done!

jhol · 2025-01-16T23:18:31Z

v3 of the patch set makes the following changes:

Fixed file copyrights
Bumped copyright year from 2024 to 2025

jhol · 2025-01-17T00:12:34Z

v4 of the patch set makes the following changes:

Fixed warnings from check_compliance.py:
- Added my name to MAINTAINERS.yml
- Fixed directory paths in MAINTAINERS.yml
- Replaced obsolete config defines:
  - CONFIG_ARCH_HAS_CPU_IDLE_CUSTOM -> CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE
  - CONFIG_ARCH_HAS_CPU_ATOMIC_IDLE_CUSTOM -> CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
- Added missing braces
- Fixed typos
- Fixed a line length issue
- Added require blank lines

jhol · 2025-01-17T00:15:57Z

v5 of the patch set makes the following changes:

Fixed warnings from check_compliance.py:
- Fixed additional blank line

PERFOPT_ALIGN is defined as ".balign 4" because .balign is available in the or1k GNU assembler. Signed-off-by: Joel Holdsworth <[email protected]>

A common set of macros: GTEXT(), GDATA(), WTEXT() and WDATA() is defined for Arm, Arm66, MIPS, Nios II, RISC-V and Xtensa. This patch adds OpenRISC to this set. Signed-off-by: Joel Holdsworth <[email protected]>

Existing versions of GEN_ABSOLUTE_SYM and GEN_ABSOLUTE_SYM_KCONFIG are defined for all supported architectures. This patch adds a definition of the same kind used for MIPS, Nios II, RISC-V and Xtensa. Signed-off-by: Joel Holdsworth <[email protected]>

The OpenRISC or1k-elf GCC compiler output format is named "elf32-or1k". This patch adds an OUTPUT_FORMAT linker macro for this platform. Signed-off-by: Joel Holdsworth <[email protected]>

Zephyr maps the start and end of the rodata section with variables using the __rodata_region_start and __rodata_region_end. This patch adopts this convention for the OpenRISC architecture. Signed-off-by: Joel Holdsworth <[email protected]>

This patch adds support for the OpenRISC 1000 (or1k) architecture: a MIPS-like open hardware ISA which was first introduced in 2000. The thread switching implementation uses the modern Zephyr thread "switch" architecture. Signed-off-by: Joel Holdsworth <[email protected]>

In OpenRISC 1000, the stack pointer is stored in the r1 register. This patch stores the offset of this value within in the thread structure into the thread info offsets. Signed-off-by: Joel Holdsworth <[email protected]>

The OpenRISC 1000 Tick Timer is tightly coupled to the or1k CPU core, and is explicitly designed to facilitate task scheduling and high-resolution timing. The timer is documented in Chapter 14 of the OpenRISC 1000 Architecture Manual: https://openrisc.io/or1k.html#__RefHeading__504849_595890882 Signed-off-by: Joel Holdsworth <[email protected]>

The Qemu emulator executable for the OpenRISC 1000 (or1k) architecture is named qemu-or1k. This patch adds this information to the qemu architecture suffix list. Signed-off-by: Joel Holdsworth <[email protected]>

Qemu includes support for the OpenRISC 1000 CPU architecture. This patch adds a Zephyr SoC definition which enables usage of this feature. The SoC definition closely mirrors the Qemu MIPS Malta SoC definition. Signed-off-by: Joel Holdsworth <[email protected]>

Qemu includes support for the OpenRISC 1000 CPU architecture. This patch adds a Zephyr virtual board definition which enables usage of this feature. The board definition closely mirrors the Qemu MIPS Malta board definition. Signed-off-by: Joel Holdsworth <[email protected]>

The OpenRISC CPU architecture is signified by the CONFIG_OPENRISC Kconfig option. This patch adds this information to the log database ARCHS table. Signed-off-by: Joel Holdsworth <[email protected]>

Adds the openrisc CPU architecture to the twister platform definitions. Signed-off-by: Joel Holdsworth <[email protected]>

The OpenRISC 1000 architecture can be tested through the qemu_or1k emulated SoC and board. Because this emulated device has minimal external hardware by default, this patch enables a minimal suite of tests covering core kernel features for the CPU architecture. When running the test suite, OpenRISC was found to require additional stack space to prevent an overflow. Therefore, a minimal additional amount of storage: 128-bytes, was added that was found in practice to allow tests to complete. Note that Qemu version 9.2.0 or newer is required so as to include the following commit: commit 3eb43aeb164f1f83c97ff693c7d464b49755110c Author: Joel Holdsworth <[email protected]> Date: Fri Jun 7 15:29:33 2024 -0700 hw/openrisc: Fixed undercounting of TTCR in continuous mode This fixes a bug in the implementation of the emulated OpenRISC Tick Timer which prevents the Zephyr OpenRISC port from task-scheduling properly. Signed-off-by: Joel Holdsworth <[email protected]>

zephyrbot · 2025-02-18T21:54:08Z

The following west manifest projects have changed revision in this Pull Request:

Name	Old Revision	New Revision	Diff
picolibc	picolibc/picolibc@`82d62ed`	picolibc/picolibc@`4380f9a` (`debian`,`1.8.9-2`)	picolibc/[email protected]

Additional metadata changed:

Name	URL	Submodules	West cmds	`module.yml`
picolibc	✏

⛔ DNM label due to: 1 project with metadata changes

Note: This message is automatically posted and updated by the Manifest GitHub Action.

jhol · 2025-02-18T21:56:12Z

Here is v8 of the patch-set with the following changes:

Rebased on main
Upgrade picolibc to the new release which officially supports OpenRISC, and no longer requires a patch via a Zephyr patch.
Replaced used of CONFIG_ISR_STACK_SIZE with __z_interrupt_all_stacks_SIZEOF in stack initialization
Fixed a typo in a comment: s/OPENRISC/OpenRISC/
Fixed instances of incorrect usage of delay slots in assembly code
Improved comments in assembly code
Fixed typos in file header comments
Set frame pointer before entering z_prep_c
Replaced the terms "vector" and "ISR" with "exception" and "exception handler" which are more appropriate for the architecture.
Renamed _Fault function to z_openrisc_fault. This change was applied to multiple other architectures in Renamed _Fault to z_${ARCH}_fault #84535
Moved interrupt handling loop into C
Added chain_call and chain_call_reg assembly macros to simplify interrupt and syscall handling code
Added __reset and __start symbols to _reset_and__start and start section as aliases of the reset exception handler
Added support for CONFIG_SOC_RESET_HOOK
Keep D and I-Cache enabled in new threads
Set FLASH_SIZE and FLASH_BASE_ADDRESS on openrisc
Fixed non-build of irq_offload.c
Fixed #ifndef _ASMLANGUAGE in arch.h
Improved linker script with more features including support for XIP

jhol · 2025-02-18T22:00:12Z

@npitre I applied your suggestion concerning __z_interrupt_stack_SIZEOF.

Concerning the timer driver, it's not so clear to me what needs to happen here. To me, the OpenRISC timer driver doesn't look so very different from the Risc-V driver, but I'm happy to make any amendments.

npitre · 2025-02-18T22:38:22Z

Concerning the timer driver, it's not so clear to me what needs to happen
here. To me, the OpenRISC timer driver doesn't look so very different from
the Risc-V driver, but I'm happy to make any amendments.

You may look at commit 0ea64b3 for explanation and the needed changes,
mainly to sys_clock_set_timeout().

Also, if your sys_clock_hw_cycles_per_sec() resolves to a constant, then
you should consider not making your cyc_per_tick into a variable otherwise
everywhere you use it as a divisor it will induce important runtime overhead.
If it is a constant then the compiler will most likely optimize the division
at compile time with much simpler ALU instructions.

nashif · 2025-02-22T12:10:06Z

@jhol I managed to build the toolchain and qemu and was trying this PR. was able to build, but did not get any output from qemu:

west build -p -b qemu_or1k samples/synchronization/ -t run -- -DCONFIG_MINIMAL_LIBC=y

picolibc did not work for me, not sure what is going on:

/home/nashif/bin/zephyr-sdk-0.17.0/or1k-zephyr-elf/bin/../lib/gcc/or1k-zephyr-elf/12.2.0/../../../../or1k-zephyr-elf/bin/ld.bfd: /home/nashif/bin/zephyr-sdk-0.17.0/or1k-zephyr-elf/bin/../lib/gcc/../../picolibc/or1k-zephyr-elf/lib/./libc.a: error adding symbols: bad value
collect2: error: ld returned 1 exit status

@keith-packard ^^

running qemu:

Memory region         Used Size  Region Size  %age Used
             RAM:       32056 B       128 MB      0.02%
        IDT_LIST:          0 GB         2 KB      0.00%
Generating files from /home/nashif/zephyrproject/zephyr/build/zephyr/zephyr.elf for board: qemu_or1k
[120/121] To exit from QEMU enter: 'CTRL+a, x'[QEMU] CPU: or1k

jhol · 2025-02-22T16:19:54Z

Thanks for testing. What version of qemu do you have?

Note that Qemu version 9.2.0 or newer is required so as to include
the following commit:

    commit 3eb43aeb164f1f83c97ff693c7d464b49755110c
    Author: Joel Holdsworth <[email protected]>
    Date: Fri Jun 7 15:29:33 2024 -0700
    hw/openrisc: Fixed undercounting of TTCR in continuous mode

This fixes a bug in the implementation of the emulated OpenRISC Tick
Timer which prevents the Zephyr OpenRISC port from task-scheduling
properly.

nashif · 2025-02-22T17:52:35Z

Thanks for testing. What version of qemu do you have?

9.2.1, you can also get it from here https://github.com/zephyrproject-rtos/sdk-ng/actions/runs/13472947957/artifacts/2635045345 (PR zephyrproject-rtos/sdk-ng#871)

jhol · 2025-02-22T18:18:48Z

Thanks for testing. What version of qemu do you have?

9.2.1, you can also get it from here https://github.com/zephyrproject-rtos/sdk-ng/actions/runs/13472947957/artifacts/2635045345 (PR zephyrproject-rtos/sdk-ng#871)

Awesome. I'll test it out when I have time in the coming days

keith-packard · 2025-02-22T21:49:41Z

/home/nashif/bin/zephyr-sdk-0.17.0/or1k-zephyr-elf/bin/../lib/gcc/or1k-zephyr-elf/12.2.0/../../../../or1k-zephyr-elf/bin/ld.bfd: /home/nashif/bin/zephyr-sdk-0.17.0/or1k-zephyr-elf/bin/../lib/gcc/../../picolibc/or1k-zephyr-elf/lib/./libc.a: error adding symbols: bad value
collect2: error: ld returned 1 exit status

I've only been testing with the debian toolchain; haven't played with this one yet, and I haven't tried zephyr yet, just the picolibc test suite.

stffrdhrn · 2025-02-23T16:55:56Z

arch/openrisc/core/reboot.c

+{
+	ARG_UNUSED(type);
+
+	__asm__("l.nop 13");


Note in QEMU the openrisc virt platform does provide reboot via the syscon-reboot device. I guess we could add support for virt later?

carlescufi · 2025-02-24T20:48:33Z

~~Hi @jhol . Would you be willing and able to present this in the Architecture WG meeting? If so, please let me know of your availability here and I will schedule a date for you.~~

My mistake, this was already presented in my absence.

henrikbrixandersen · 2025-02-25T08:52:32Z

Architecture WG 2025-02-18:

@jhol gave a good introduction to the proposed port of Zephyr to the OpenRISC architecture.
NVIDIA is interested in backing this architecture port, and expect to be able to back it for at least 5 years.
The Zephyr SDK need to be updated to support the OpenRISC architecture (compiler suite, emu, …).

zephyrbot requested review from aaronemassey, andyross, asemjonovs, ceolin, cfriedt, dcpleung, jeremybettis, nashif, npitre, peter-mitsis, stephanosio, TaiJuWu, teburd, tejlmand and yperess January 14, 2025 00:31

zephyrbot assigned dcpleung and nashif Jan 14, 2025

kartben added the area: Boards label Jan 16, 2025

jhol force-pushed the or1k-port branch from 9530f8b to d3ae553 Compare January 16, 2025 22:51

jhol force-pushed the or1k-port branch from d3ae553 to 5dbae60 Compare January 16, 2025 23:17

jhol force-pushed the or1k-port branch from 5dbae60 to 339eefb Compare January 17, 2025 00:08

jhol force-pushed the or1k-port branch from 339eefb to 9491bf8 Compare January 17, 2025 00:15

jhol added 14 commits February 18, 2025 11:00

toolchain: common: Define PERFOPT_ALIGN for OpenRISC

f006e8f

PERFOPT_ALIGN is defined as ".balign 4" because .balign is available in the or1k GNU assembler. Signed-off-by: Joel Holdsworth <[email protected]>

toolchain: gcc: Added symbol attributes for OpenRISC

f040627

A common set of macros: GTEXT(), GDATA(), WTEXT() and WDATA() is defined for Arm, Arm66, MIPS, Nios II, RISC-V and Xtensa. This patch adds OpenRISC to this set. Signed-off-by: Joel Holdsworth <[email protected]>

toolchain: gcc: Define output format for or1k-elf

82116f6

The OpenRISC or1k-elf GCC compiler output format is named "elf32-or1k". This patch adds an OUTPUT_FORMAT linker macro for this platform. Signed-off-by: Joel Holdsworth <[email protected]>

cmake: emu: qemu: Add binary suffix for or1k architecture

0be2565

The Qemu emulator executable for the OpenRISC 1000 (or1k) architecture is named qemu-or1k. This patch adds this information to the qemu architecture suffix list. Signed-off-by: Joel Holdsworth <[email protected]>

scripts: logging: Add openrisc to ARCHS

2b01b95

The OpenRISC CPU architecture is signified by the CONFIG_OPENRISC Kconfig option. This patch adds this information to the log database ARCHS table. Signed-off-by: Joel Holdsworth <[email protected]>

scripts: twister: Add OpenRISC as a supported test platform

3d93de1

Adds the openrisc CPU architecture to the twister platform definitions. Signed-off-by: Joel Holdsworth <[email protected]>

jhol force-pushed the or1k-port branch from 2b2a77d to 2f64a88 Compare February 18, 2025 21:49

zephyrbot added manifest manifest-picolibc DNM (manifest) This PR should not be merged (controlled by action-manifest) labels Feb 18, 2025

stffrdhrn reviewed Feb 23, 2025

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arch: Added initial OpenRISC port #83933

arch: Added initial OpenRISC port #83933

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