This resource comes from UCSD’s 237C Parallel Programming for FPGAs. Currently, I am trying to finish this tutorial through vitis_hls 2020.
reference: https://pp4fpgas.readthedocs.io/en/latest/index.html
FPGA board: PYNQ TUL-Z2
EDA tool: Vivado 2020.2, Vitis_HLS 2020.2, Vivado 2021.1, Vitis_HLS 2021.1
| protocol | Vitis_HLS folder | Vivado folder | |
|---|---|---|---|
| Lab 1: Pynq Memory Mapped IO | AXI4 lite | Mul | mul_v |
| Lab 2: Axistream Single DMA | AXI4 Stream | StreamMul | smul_v |
| Lab 3: Axistream Multiple DMAs | AXI4 Stream | StreamAdd | sadd_v |
| Lab 4: AXI4-Burst Mode | AXI4 Master | axi4_burst | axi_sqrt_v |
| Project 1: Discrete Fourier Transform (DFT) | AXI4 Master | DFT | DFT_v |