A digital clock system implemented with VHDL via Intel Quartus Prime and ModelSim.
- Testing the reset functionality: When the reset signal is asserted, the clock's time components (seconds, minutes, and hours) are set to zero, ensuring a fresh start and providing a reliable baseline for timekeeping.
- Testing the seconds incrementation: The testing of the seconds incrementation in the digital clock was successful, as observed in the waveform where the seconds component incremented correctly at each rising edge of the clock signal, validating its accurate timekeeping functionality.
- Testing the minutes incrementation: It was observed that the minutes incremented correctly at each rising edge of the clock signal, after the second counter completed 59 counts, confirming the reliable functionality of the clock.
- Testing the hours Incrementation: The observed waveform demonstrated that the hours were consistently incremented with precision reliably after the count of 59 minutes.
- Testing the reset after the 24 hour count: By simulating the clock operation for a full 24-hour period and asserting the reset signal, the waveform was analyzed to ensure the clock properly reset to 1 and the rest of inputs and outputs to 0, allowing for seamless continuation of timekeeping beyond 24 hours.
