LOROF: Linux-on-RISCV-on-FPGA
Goal is to design, verify, and implement on FPGA a RISC-V RV32IMA_Zicsr_Zifencei Sv32 Quad-Core Superscalar Out-of-Order CPU, successfully booting and running Linux.
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Linux-on-RISCV-on-FPGA. Goal is to design, verify, and implement on FPGA a RISC-V RV32IMA_Zicsr_Zifencei implementation with supervisor and user mode support, successfully booting and running Linux with documentation, RTL code and UVM based testbenches.
AdamKeith1/LOROF
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Linux-on-RISCV-on-FPGA. Goal is to design, verify, and implement on FPGA a RISC-V RV32IMA_Zicsr_Zifencei implementation with supervisor and user mode support, successfully booting and running Linux with documentation, RTL code and UVM based testbenches.
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