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applet.display.hd44780: modify to use port groups. #604

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Jun 27, 2024
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applet.display.hd44780: modify to use port groups. #604

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42 changes: 23 additions & 19 deletions software/glasgow/applet/display/hd44780/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@
import logging
import asyncio
from amaranth import *
from amaranth.lib.cdc import FFSynchronizer
from amaranth.lib import io, cdc

from ... import *

Expand Down Expand Up @@ -61,8 +61,8 @@


class HD44780Subtarget(Elaboratable):
def __init__(self, pads, out_fifo, in_fifo, sys_clk_freq):
self.pads = pads
def __init__(self, ports, out_fifo, in_fifo, sys_clk_freq):
self.ports = ports
self.out_fifo = out_fifo
self.in_fifo = in_fifo
self.sys_clk_freq = sys_clk_freq
Expand All @@ -72,13 +72,12 @@ def elaborate(self, platform):

di = Signal(4)

m.d.comb += [
self.pads.rs_t.oe.eq(1),
self.pads.rw_t.oe.eq(1),
self.pads.e_t.oe.eq(1),
self.pads.d_t.oe.eq(~self.pads.rw_t.o),
]
m.submodules += FFSynchronizer(self.pads.d_t.i, di)
m.submodules.rs_buffer = rs_buffer = io.Buffer("o", self.ports.rs)
m.submodules.rw_buffer = rw_buffer = io.Buffer("o", self.ports.rw)
m.submodules.e_buffer = e_buffer = io.Buffer("o", self.ports.e)
m.submodules.d_buffer = d_buffer = io.Buffer("io", self.ports.d)
m.d.comb += d_buffer.oe.eq(~rw_buffer.o),
m.submodules += cdc.FFSynchronizer(d_buffer.i, di)

rx_setup_cyc = math.ceil(60e-9 * self.sys_clk_freq)
e_pulse_cyc = math.ceil(500e-9 * self.sys_clk_freq)
Expand All @@ -93,7 +92,7 @@ def elaborate(self, platform):

with m.FSM() as fsm:
with m.State("IDLE"):
m.d.sync += self.pads.e_t.o.eq(0)
m.d.sync += e_buffer.o.eq(0)
m.d.comb += self.out_fifo.r_en.eq(1)
with m.If(self.out_fifo.r_rdy):
m.d.sync += cmd.eq(self.out_fifo.r_data)
Expand All @@ -102,8 +101,8 @@ def elaborate(self, platform):
with m.State("COMMAND"):
m.d.sync += [
msb.eq((cmd & XFER_BIT_HALF) == 0),
self.pads.rs_t.o.eq((cmd & XFER_BIT_DATA) != 0),
self.pads.rw_t.o.eq((cmd & XFER_BIT_READ) != 0),
rs_buffer.o.eq((cmd & XFER_BIT_DATA) != 0),
rw_buffer.o.eq((cmd & XFER_BIT_READ) != 0),
]
with m.If(cmd & XFER_BIT_WAIT):
m.d.sync += timer.eq(cmd_wait_cyc)
Expand All @@ -120,8 +119,8 @@ def elaborate(self, platform):
with m.State("WRITE"):
with m.If(timer == 0):
m.d.sync += [
self.pads.e_t.o.eq(1),
self.pads.d_t.o.eq(Mux(msb, wdata[4:], wdata[:4])),
e_buffer.o.eq(1),
d_buffer.o.eq(Mux(msb, wdata[4:], wdata[:4])),
timer.eq(e_pulse_cyc),
]
m.next = "WRITE-HOLD"
Expand All @@ -131,7 +130,7 @@ def elaborate(self, platform):
with m.State("WRITE-HOLD"):
with m.If(timer == 0):
m.d.sync += [
self.pads.e_t.o.eq(0),
e_buffer.o.eq(0),
msb.eq(0),
timer.eq(e_wait_cyc),
]
Expand All @@ -145,7 +144,7 @@ def elaborate(self, platform):
with m.State("READ-SETUP"):
with m.If(timer == 0):
m.d.sync += [
self.pads.e_t.o.eq(1),
e_buffer.o.eq(1),
timer.eq(e_pulse_cyc),
]
m.next = "READ"
Expand All @@ -159,7 +158,7 @@ def elaborate(self, platform):
pass
with m.Else():
m.d.sync += [
self.pads.e_t.o.eq(0),
e_buffer.o.eq(0),
msb.eq(0),
timer.eq(e_wait_cyc),
]
Expand Down Expand Up @@ -218,7 +217,12 @@ def add_build_arguments(cls, parser, access):
def build(self, target, args):
self.mux_interface = iface = target.multiplexer.claim_interface(self, args)
iface.add_subtarget(HD44780Subtarget(
pads=iface.get_deprecated_pads(args, pins=("rs", "rw", "e"), pin_sets=("d",)),
ports=iface.get_port_group(
rs=args.pin_rs,
rw=args.pin_rw,
e=args.pin_e,
d=args.pin_set_d,
),
out_fifo=iface.get_out_fifo(),
in_fifo=iface.get_in_fifo(),
sys_clk_freq=target.sys_clk_freq,
Expand Down
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