Xlnx ipm demo split #4
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Signed-off-by: Tanmay Shah <[email protected]>
Xilinx ZynqMP platform has cortex-r5 cluster which can be configured in lockstep or split mode. In lockstep mode only one core is available where as in split mode two cores can run independently in AMP mode. Introduce dtsi files for RPU core0 and core1 to include separtely in case application is being built for Asynchronous MultiProcessing use. Signed-off-by: Tanmay Shah <[email protected]>
demonstrate ipm API use with AMD-xilinx ipm driver. Two samples are introduced. Sample in rpu_core0 directory should be flashed on core 0 first and then rpu_core1 should be flashed on core 1. RPU core0 programms gic controller so it has to run first as of now. This limitation should be removed in future. Signed-off-by: Tanmay Shah <[email protected]>
fix gic interrupt controller to work in AMP mode GIC controller is working only in SMP mode, add support of AMP mode. Signed-off-by: Tanmay Shah <[email protected]>
Xilinx ZynqMP platform has cortex-r5 cluster which can be configured in lockstep or split mode. In lockstep mode only one core is available where as in split mode two cores can run independently in AMP mode. Introduce dtsi files for RPU core0 and core1 to include separtely in case application is being built for Asynchronous MultiProcessing use. Signed-off-by: Tanmay Shah <[email protected]>
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Add support of Xilinx R5 in split mode.
This PR is only for explaining problems and design reviews, and do not compile.
Must not merge, Only draft PR.