Xlnx ipm demo split

boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts

@@ -6,7 +6,7 @@
  */
 
 /dts-v1/;
-#include <arm/xilinx/zynqmp_rpu.dtsi>
+#include <arm/xilinx/zynqmp_rpu0.dtsi>
 
 / {
 	model = "QEMU Cortex-R5";
@@ -15,19 +15,19 @@
 	chosen {
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
 		zephyr,ocm = &ocm;
 	};
 };
 
-&uart0 {
+&uart1 {
 	status = "okay";
 	current-speed = <115200>;
 	clock-frequency = <99999901>;
 };
 
-&ttc0 {
+&ttc1 {
 	status = "okay";
 	clock-frequency = <5000000>;
 };

boards/arm/qemu_cortex_r5/qemu_cortex_r5_defconfig

@@ -13,5 +13,6 @@ CONFIG_SERIAL=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=500000000
 CONFIG_ARM_MPU=y

drivers/interrupt_controller/intc_gic.c

@@ -26,21 +26,40 @@ BUILD_ASSERT(ARRAY_SIZE(cpu_mpid_list) >= CONFIG_MP_MAX_NUM_CPUS,
 
 void arm_gic_irq_enable(unsigned int irq)
 {
+	uint8_t cpu_mask = 0;
+	uint8_t *itarget_reg;
 	int int_grp, int_off;
 
 	int_grp = irq / 32;
 	int_off = irq % 32;
 
+	itarget_reg = (uint8_t *)(GICD_ITARGETSRn);
+	itarget_reg += irq;
+
+	cpu_mask = BIT(cpu_mpid_list[0]);
+
+	sys_write8(cpu_mask, (mem_addr_t)itarget_reg);
+
 	sys_write32((1 << int_off), (GICD_ISENABLERn + int_grp * 4));
 }
 
 void arm_gic_irq_disable(unsigned int irq)
 {
 	int int_grp, int_off;
+	uint8_t cpu_mask = 0, reg_val = 0;
+	uint8_t *itarget_reg;
 
 	int_grp = irq / 32;
 	int_off = irq % 32;
 
+	itarget_reg = (uint8_t *)(GICD_ITARGETSRn);
+	itarget_reg += irq;
+	cpu_mask = BIT(cpu_mpid_list[0]);
+
+	reg_val = sys_read8((mem_addr_t)itarget_reg);
+	reg_val &= (~cpu_mask);
+
+	sys_write8(reg_val, (mem_addr_t)itarget_reg);
 	sys_write32((1 << int_off), (GICD_ICENABLERn + int_grp * 4));
 }
 
@@ -146,20 +165,14 @@ static void gic_dist_init(void)
 {
 	unsigned int gic_irqs, i;
 	uint8_t cpu_mask = 0;
-	uint32_t reg_val;
+	uint32_t reg_val, val;
 
 	gic_irqs = sys_read32(GICD_TYPER) & 0x1f;
 	gic_irqs = (gic_irqs + 1) * 32;
 	if (gic_irqs > 1020) {
 		gic_irqs = 1020;
 	}
 
-	/*
-	 * Disable the forwarding of pending interrupts
-	 * from the Distributor to the CPU interfaces
-	 */
-	sys_write32(0, GICD_CTLR);
-
 	/*
 	 * Enable all global interrupts distributing to CPUs listed
 	 * in dts with the count of arch_num_cpus().
@@ -171,10 +184,23 @@ static void gic_dist_init(void)
 	}
 	reg_val = cpu_mask | (cpu_mask << 8) | (cpu_mask << 16)
 		| (cpu_mask << 24);
+
 	for (i = GIC_SPI_INT_BASE; i < gic_irqs; i += 4) {
-		sys_write32(reg_val, GICD_ITARGETSRn + i);
+		val = sys_read32(GICD_ITARGETSRn + i);
+		val &= ~(reg_val);
+		sys_write32(val, GICD_ITARGETSRn + i);
 	}
 
+	/* another core has already initialized interrupts */
+	if ((sys_read32(GICD_CTLR) & 0x1) == 1)
+		return;
+
+	/*
+	 * Disable the forwarding of pending interrupts
+	 * from the Distributor to the CPU interfaces
+	 */
+	sys_write32(0, GICD_CTLR);
+
 	/*
 	 * Set all global interrupts to be level triggered, active low.
 	 */

dts/arm/xilinx/zynqmp.dtsi

@@ -23,7 +23,7 @@
 
 		ocm: memory@fffc0000 {
 			compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
-			reg = <0xfffc0000 DT_SIZE_K(256)>;
+			reg = <0xfffc0000 DT_SIZE_K(128)>;
 			zephyr,memory-region = "OCM";
 		};
 

dts/arm/xilinx/zynqmp_rpu.dtsi

@@ -4,21 +4,56 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <arm/xilinx/zynqmp.dtsi>
+#include <mem.h>
+#include <arm/armv7-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
 
 / {
-	cpus {
+	cpus: cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
+			status = "okay";
 			device_type = "cpu";
 			compatible = "arm,cortex-r5f";
 			reg = <0>;
 		};
+
+		cpu1: cpu@1 {
+			status = "disabled";
+			device_type = "cpu";
+			compatible = "arm,cortex-r5f";
+			reg = <0>;
+		};
+
+		cpu1: cpu@1 {
+			status = "disabled";
+			device_type = "cpu";
+			compatible = "arm,cortex-r5f";
+			reg = <1>;
+		};
 	};
 
-	soc {
+	soc: soc {
+
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@f9000000 {
+			compatible = "arm,gic-v1", "arm,gic";
+			reg = <0xf9000000 0x1000>,
+					<0xf9001000 0x100>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+
+		ocm: memory@fffe0000 {
+			compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
+			reg = <0xfffe0000 DT_SIZE_K(128)>;
+			zephyr,memory-region = "OCM";
+		};
 
 		rpu0_ipi: zynqmp-ipi@ff310000 {
 			status = "disabled";
@@ -96,15 +131,39 @@
 			};
 		};
 
-		interrupt-parent = <&gic>;
+		ttc1: timer@ff120000 {
+			compatible = "xlnx,ttcps";
+			status = "disabled";
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "irq_0", "irq_1", "irq_2";
+			reg = <0xff120000 0x1000>;
+		};
 
-		gic: interrupt-controller@f9000000 {
-			compatible = "arm,gic-v1", "arm,gic";
-			reg = <0xf9000000 0x1000>,
-					<0xf9001000 0x100>;
-			interrupt-controller;
-			#interrupt-cells = <4>;
-			status = "okay";
+		ttc2: timer@ff130000 {
+			compatible = "xlnx,ttcps";
+			status = "disabled";
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "irq_0", "irq_1", "irq_2";
+			reg = <0xff130000 0x1000>;
+		};
+
+		uart1: uart@ff010000 {
+			compatible = "xlnx,xuartps";
+			reg = <0xff010000 0x4c>;
+			status = "disabled";
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "irq_0";
 		};
 	};
 };

dts/arm/xilinx/zynqmp_rpu0.dtsi

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Stephanos Ioannidis <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/xilinx/zynqmp_rpu.dtsi>
+
+&soc {
+	flash0: flash@3ed00000 {
+		compatible = "soc-nv-flash";
+		reg = <0x3ed00000 DT_SIZE_K(256)>;
+	};
+
+	sram0: memory@0 {
+		compatible = "mmio-sram";
+		reg = <0 DT_SIZE_M(64)>;
+	};
+};
+
+&cpu0 {
+	status = "okay";
+};
+
+&cpu1 {
+	status = "disabled";
+};
+
+&rpu0_ipi {
+	status = "okay";
+};
+
+&ttc1 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};

dts/arm/xilinx/zynqmp_rpu1.dtsi

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2019 Stephanos Ioannidis <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/xilinx/zynqmp_rpu.dtsi>
+
+&soc {
+	flash1: flash@3ef00000 {
+		compatible = "soc-nv-flash";
+		reg = <0x3ef00000 DT_SIZE_K(256)>;
+	};
+
+	sram1: memory@0 {
+		compatible = "mmio-sram";
+		reg = <0 DT_SIZE_M(64)>;
+	};
+};
+
+&cpu0 {
+	status = "disabled";
+};
+
+&cpu1 {
+	status = "okay";
+};
+
+&rpu1_ipi {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&ttc2 {
+	status = "okay";
+};

samples/drivers/ipm/ipm_xlnx/rpu_core0/CMakeLists.txt

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(ipm_xlnx)
+
+target_include_directories(app PRIVATE ${ZEPHYR_BASE}/drivers)
+target_sources(app PRIVATE src/main.c)

samples/drivers/ipm/ipm_xlnx/rpu_core0/boards/qemu_cortex_r5.overlay

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2019 Lexmark International, Inc.
+ * Copyright (c) 2023 AMD-Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <arm/xilinx/zynqmp_rpu0.dtsi>
+
+/ {
+	model = "QEMU Cortex-R5";
+	compatible = "xlnx,zynqmp-qemu";
+
+	chosen {
+		zephyr,flash = &flash0;
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+	};
+};
+
+&rpu0_ipi {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <99999901>;
+};
+
+&ttc1 {
+	status = "okay";
+	clock-frequency = <500000000>;
+};

samples/drivers/ipm/ipm_xlnx/rpu_core0/prj.conf

@@ -0,0 +1,6 @@
+CONFIG_STDOUT_CONSOLE=n
+CONFIG_PRINTK=y
+CONFIG_IPM=y
+CONFIG_XLNX_IPI=y
+CONFIG_XLNX_PSTTC_TIMER_INDEX=1
+CONFIG_SERIAL_INIT_PRIORITY=35

samples/drivers/ipm/ipm_xlnx/rpu_core0/sample.yaml

@@ -0,0 +1,9 @@
+sample:
+  description: Xilinx IPI mailbox driver
+tests:
+  sample.ipm.ipm_xlnx:
+    build_only: true
+    platform_allow: qemu_cortex_r5
+    integration_platforms:
+      - qemu_cortex_r5
+    tags: samples ipm